FM8PC71AM datasheet(3/73 Pages) FEELING

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FM8PC71AM

This datasheet contains new product information. Feeling Technology reserves the rights to modify the product specification without notice.

No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.

P.3

R1.1.004, Aug 7, 2017

FM8PC71AM

遠翔科技

Feeling Technology

Contents

【1】FM8PC71AM REVIEW ................................................................................................ 7

1.1 General Description.............................................................................................. 7

1.2 Features ................................................................................................................ 7

1.3 Block Diagram ..................................................................................................... 8

1.4 Pin Definitions...................................................................................................... 8

1.5 Pin Description ..................................................................................................... 9

1.6 Program Memory Mapping ................................................................................ 11

1.7 Memory And Register Mapping......................................................................... 11

1.8 Register bit Mapping .......................................................................................... 12

1.9 Table of Optional configuration ......................................................................... 15

【2】Macro-Controller UNIT .............................................................................................. 16

2.1 Indirect Addressing Define................................................................................. 16

Address 00H: Indirect Addressing Register (INDF) ........................................ 16

Address 04H: File select Register(FSR) .......................................................... 16

2.2 Program Counter least significant 8 bits ............................................................ 17

Address 02H: Low bytes of Program Counter(PCL) ....................................... 17

2.3 Status Register .................................................................................................... 18

Address 03H: Status Register(STATUS).......................................................... 18

2.4 General Purpose I/O ports .................................................................................. 19

2.4.1 PortA, PortB data define ......................................................................... 19

Address 05H: Port A(PORTA) ......................................................................... 19

Address 06H: Port B(PORTB) ......................................................................... 19

2.4.2

PortA, PortB Interrupt define ........................................................... 20

Address 07H: Port A Interrupt Control Register(PAIE) ................................... 20

Address 08H: Port B Interrupt Control Register(PBIE)................................... 20

Address 09H: Port A Wake-Up Control Register(PACON) ............................. 21

Address 0AH: Port B Wake-Up Control Register(PACON) ............................ 22

2.4.3 PortA, PortB Mode define....................................................................... 23

Address 08H: Port A Mode0 Control Register(PAMODE0)............................ 23

Address 09H: Port A Mode1 Control Register(PAMODE1)............................ 23

Address 0AH: Port B Mode1 Control Register(PBMODE0) .......................... 23

Address 0BH: Port B Mode1 Control Register(PBMODE1)........................... 23

2.5 Watchdog Timer(WDT)...................................................................................... 25

Address 11H: Watchdog Timer(WDT)............................................................. 25

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