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NM1482KSLAXCL Datasheet(PDF) 12 Page - Nanya Technology Corporation. |
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NM1482KSLAXCL Datasheet(HTML) 12 Page - Nanya Technology Corporation. |
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12 / 119 page  Version 1.3 12 Nanya Technology Corp. 06/2018 All Rights Reserved. © 4Gb SLC NAND + 2Gb LPDDR2 NM1482KSLAXCL NTC Proprietary Level: Property Function Block Diagram (X8) Schematic Cell Layout and Address Assignment (X8) The Program operation works on page units while the Erase operation works on block units Array Address (X8) I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 Address 1st cycle CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 Column Address 2nd cycle CA8 CA9 CA10 CA11 CA12 L L L Column Address 3rd cycle PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 Page Address 4th cycle PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 Page Address 5th cycle PA16 L L L L L L L Page Address PA6 to PA16: Block address PA0 to PA5: NAND address in block A page consists of 4352 bytes in which 4096 bytes are used for main memory storage and 256 bytes are for redundancy or for other uses. 1 Page = 4352 Bytes 1 Block = 4352 Bytes x 64 Pages = (256K + 16K) Bytes Capacity = 4352 Bytes x 64 Pages x 2048 Blocks RY/ CLE ALE [ 鍵 入 文 件 的 引 文 或 重 點 的 摘 要 。 您 可 以 將 文 字 方 塊 放 在 文 件 中 的 VCC VSS I/O Control circuit Logic control Control circuit HV generator RY/ I/O 0 to I/O 7 Address register Status register Command register Memory cell array Command register Data register Column decoder Column buffer 1 Block = 64 Pages (256K + 16K) Bytes I/O 7 I/O 0 |
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