GPLB30A

© Generalplus Technology Inc.

Proprietary & Confidential

4

JAN. 07, 2008

Version: 1.4

4. BLOCK DIAGRAM

RC-Oscillator

System Clock Gen.

Power Supply

Voltage Detect

96K bytes

ROM

2752

bytes

RAM

Two 16-bit /

Auto-reload

Timers

32 KHz

Oscillator

&

Time

base

8-bit

micro-

processor

UART

PWM Driver

Max.29

I/O Ports

16 Commons X 70 Segments LCD Driver

32KHz

ROSC

Rx/PC3

Tx/PC2

AUDA

COM[15:0]

SEG[69:0]

LCD RAM 148 bytes

ROSC32

AUDB

Serial SRAM

I/F

SDA/PC1

SCK/PC0

BUS Mem I/F

MC[1:0]/PC[1:0]

AD[7:0]/PB[7:0]

8

2

PA[7:0]

(I/O)

PB[7:0]

PC[7:0]

PD[4:0]

5

8

8

8

Voltage

Regulator

VROUT

Note1: PA[5:7] share pins with SEG[69:67] (mask option).

Note2: PB[0:7] share pins with SEG[64:57] (mask option).

Note3: PC[0:1] share pins with Bus memory interface MC[0:1].

Also share pins with Serial SRAM interface SCK/SDA.

Note4:PC[2:3] share pins with UART Tx/Rx. Also share pins with SEG[66:65].

Note5: PC[4:7] share pins with SEG[56:53] (mask option).

Note6: PD[0:4] share pins with SEG[52:48] (mask option).