GPLB30A datasheet(8/20 Pages) GENERALPLUS

8 / 20 page

GPLB30A

Proprietary & Confidential

JAN. 07, 2008

Version: 1.4

The following figure is the GPLB30A state diagram:

GPLB30A State Diagram

6.4. Speech and Melody

For speech synthesis, the GPLB30A provides several timer

interrupts for a precise sampling frequency.

The sound data can

be stored into ROM and be played back.

Several algorithms are

recommended for high fidelity and good compression of sound

such as PCM and ADPCM.

For melody synthesis, the GPLB30A provides a dual tone mode.

Once in the dual tone mode, users only need to program the tone

frequency for each channel by writing to the timer/counter TM0

and TM1, and set the envelope of each channel.

The hardware

will toggle the tone wave automatically.

6.5. LCD Controller/Driver

The GPLB30A contains an 1120-dot LCD controller/driver.

programmer is able to define the LCD configuration by setting up

the LCD Control Register.

Once the LCD configuration is

completed, the desired pattern can be displayed by filling the LCD

buffer with proper data.

The LCD driver can also operate during

sleep by keeping 32768 oscillator running.

The LCD driver in

GPLB30A supports 1/16 duty and 1/5 bias.

6.6. LCD Voltage Generation

The GPLB30A offers a voltage regulator and a charge-pumping

circuit.

The voltage regulator provides a reference voltage (V2)

for the charge-pumping circuit to generate VLCD.

Users can get

the desired VLCD by changing the output reference voltage

(writing to register) of the voltage regulator.

Enabling the voltage

regulator and charge-pumping circuit gets a stable VLCD that will

not be affected by VDD.

The VLCD is adjustable from 2.45V to

5.75V with 32 levels.

6.7. PWM Output

Internally, the GPLB30A has a pair of PWM drivers, supporting two

sound channels.

Each channel is able to play speech or tone

individually.

The PWM drivers can directly drive speaker or

buzzer without buffer or amplification circuit.

HALT

OPERATING

STANDBY

Write $07h to

CPU_Clk_Ctrl register,

32768 oscillator OFF

Wake-up or user reset

6.8. Serial SRAM Interface

The Serial SRAM interface is able to expand the data storage

SRAM.

The Control Registers are ranged from $30-$36.

Note

that The pins of SDA and SCK are shared with PC [1:0] and

therefore, users should set PC[1:0] as Serial SRAM interface by

writing to Port $27[1:0].

SDA

SCK

change of data

allowed

data line

stable;

data valid

START condition (S)

SDA

SCK

STOP condition (P)

6.8.1. Read/Write timing

R/W A23

D6 D5 D4 D3 D2 D1 D0

SDA

SCK

stop

start

6.8.2. Continuous Read/Write timing

R/W A23

D0 D7

SDA

SCK

addr

stop

start

addr+1

addr+n

6.9. Bus Memory Interface

A built-in Bus memory interface is available on GPLB30A.

Through the use of Bus memory interface, user can expand the

memory space by using a external Bus memory (SRAM, mask

ROM or Flash).

The Bus memory interface includes 10 signal

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