GPLB30A datasheet(9/20 Pages) GENERALPLUS

9 / 20 page

GPLB30A

Proprietary & Confidential

JAN. 07, 2008

Version: 1.4

pins: MC1, MC0 and AD BUS[7:0] which shared pin with port B.

Before using the Bus memory interface, users should set MEXT=1

($03.7) and BANK register ($0), then access address $4000-BFFF

to read or write data from external bus memory.

Note that when

using Bus memory interface, CPU clock setting can not be set as

FOSC/1, should be /2 or slower.

MC1

MC0

AD BUS [7:0]

Data for Write

Data for Read

AL (Address Low byte)

AH (Address High byte)

The simple timing relation is as follows:

6.10. Voltage Regulator

The GPLB30A offers a voltage regulator, which supplies power

source for external memory devices.

The voltage regulator can

output four voltage levels, 2.5V/2.6V/2.7V/3.0V via bonding option.

The output voltage level should be properly selected based on the

electrical characteristics of external memory devices involved.

6.11. Asynchronous Serial Interface (UART)

The

GPLB30A

supports

1-channel

UART

for

serial

communications.

The bit-rate is up to 115.2kbps.

UART

operation

controlled

UART

command

registers.

Configurations such as Tx/Rx interrupt, parity check, parity

even/odd and clock source can be configured in the command

registers.

Two interrupts are generated by Rx and Tx.

The Rx

or Tx interrupt activates when a byte is received or transmitted.

Reading the status register informs whether the interrupt is

generated by Rx or Tx.

Frame, overrun and parity errors are

detected as each byte is received and all error status can be read

from status register.

The UART supports clock auto calibration.

If auto calibration is

selected, standard baud rate from 1.2kbps to 115.2kbps are

available.

The baud rate is selected by writing to the baud rate

control registers.

The supported baud rates and their minimum

R-oscillator clock frequency requirements are shown in the table

below.

Baud Rate(bps)

Min. Frosc(Hz)

1200

24000

2400

48000

4800

96000

9600

192000

19200

384000

38400

768000

51200

1024000

57600

1152000

102400

2048000

115200

2304000

MC0

Read Cycle:

MC1

DATA for read

Write Cycle:

MC0

MC1

DATA for read

If the auto calibration is not selected, users can get desired baud

rates by writing appropriate values to pre-scalar registers.

Non-standard baud rates can be obtained by this method.

In the

non-calibration

mode,

users

should

understand

that

the

R-oscillator frequency may alter due to manufacturing process

variations, supply voltage, operating temperature and tolerance of

external R components used.

6.12. Low Voltage Detection

The GPLB30A provides an 8-level (Software programmable) low

voltage detector to detect low voltage events.

Users can turn on

the low detection to monitor VDD periodically to check if it is lower

than the given value.

In addition, if LV NMI is enabled, a NMI will

be issued to notify CPU if power voltage drops below the given

value.

Also, the voltage detector will generate a system reset if

power supply voltage drops below 2.2V.

When LVR function is

enabled, care must be taken not to turn off 32kHz crystal oscillator.

Otherwise an unexpected reset may occur when 32kHz crystal is

being turned on again.

6.13. Key Scan Function

GPLB30A supports key scan function.

The LCD driver will

generate a key strobe signal in the period of every common.

When PA received this strobe signal, a wake-up is issued.

Then

users can send the key scan signal through SEG[15:0] to

determine the location of the depressed key.

6.14. Watchdog Timer (WDT)

An on chip watchdog timer is also available in the GPLB30A.

The WDT is designed to recover the system from abnormal

operation.

In some cases, if WDT is not cleared for one second,

the WDT will generate a system reset to restart system.

If WDT

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