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S1M8822X01-R0T0 Datasheet(PDF) 12 Page - Samsung semiconductor |
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S1M8822X01-R0T0 Datasheet(HTML) 12 Page - Samsung semiconductor |
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12 / 22 page ![]() S1M8821/22/23 INTERGER RF/IF DUAL PLL 12 ELECTRICAL CHARACTERISTICS (Continued) (VDD=3.0V, VP=3.0V, Ta = === 25°C, Unless otherwise specified ) <For Charge Pump items> Ia=Charge pump sink current at Vcp=Vp- ∆V, Ib=Charge pump sink current at Vcp=Vp/2, Ic=Charge pump sink current at Vcp= ∆V Id=Charge pump source current at Vcp=Vp- ∆V, Ie=Charge pump source current at Vcp=Vp/2, If=Charge pump source current at Vcp= ∆V ∆V=Voltage offset from positive(for sink current) and negative(for source current) points from which the charge pump currents become flat. * Output Current Sink vs. Source Mismatch = [| Ib|-|Ie|] / [0.5 * {| Ib|+|Ie|}] * 100 (%) ** Output Current Magnitude Variation vs. Temperature = [| Ib @any temp.| - |Ib @ 25 οC|] / | Ib @ 25οC| * 100 (%) and [|Ie @any temp.| - |Ie @ 25οC|] / |Ie @ 25οC| * 100 (%) *** Output Current Magnitude Variation vs. Voltage = [0.5 * {|Ia|-|Ic|}] / [0.5 * {|Ia|+|Ic|}] * 100 (%) and [0.5 * {|Id|-|If|}] / [0.5 * {|Id|+|If|}] * 100 (%) Characteristic Symbol Test Conditions Min. Typ. Max. Unit Serial Data Control CLOCK Frequency fCLOCK 10 MHz CLOCK Pulse Width High tCWH 50 ns CLOCK Pulse Width Low tCWL 50 ns DATA Set Up Time to CLOCK Risng Edge tDS 50 ns DATA Hold Time after CLOCK Rising Edge tDH 10 ns LE Pulse Width tLEW 50 ns CLOCK Rising Edge to LE Rising Edge tCLE 50 ns |
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