CY2287
6
CY2287 Switching Characteristics[8] Over the Operating Range
Parameter
Output
Description
Test Conditions
Min.
Max.
Unit
t1
All
Output Duty Cycle[9]
t1A/(t1A + t1B)
45
55
%
t2
CPU, APIC
Rising Edge Rate
Between 0.4V and 2.0V
1.0
4.0
V/ns
t2
USB, REF
Rising Edge Rate
Between 0.4V and 2.4V
0.5
2.0
V/ns
t2
PCI, 3V66
Rising Edge Rate
Between 0.4V and 2.4V
1.0
4.0
V/ns
t2
SDRAM
Rising Edge Rate
Between 0.4V and 2.4V
1.0
4.0
V/ns
t3
CPU, APIC
Falling Edge Rate
Between 2.0V and 0.4V
1.0
4.0
V/ns
t3
USB, REF
Falling Edge Rate
Between 2.4V and 0.4V
0.5
2.0
V/ns
t3
PCI, 3V66
Falling Edge Rate
Between 2.4V and 0.4V
1.0
4.0
V/ns
t3
SDRAM
Falling Edge Rate
Between 2.4V and 0.4V
1.0
4.0
V/ns
t4
CPU
CPU-CPU Skew
Measured at 1.25V
175
ps
t4
SDRAM
SDRAM-SDRAM Skew
Measured at 1.5V
250
ps
t4
APIC
APIC-APIC Skew
Measured at 1.25V
250
ps
t4
PCI
PCI-PCI Skew
Measured at 1.5V
500
ps
t4
3V66
3V66-3V66 Skew
Measured at 1.5V
175
ps
t4
3V66, PCI
3V66-PCI Clock Skew
3V66 leads[10]
1.5
4.0
ns
t4
APIC, PCI
APIC-PCI Clock Skew
Coincident every edge[10, 11]
500
ps
t5
SDRAM, 3V66
SDRAM-3V66 Clock Skew
Coincident every other 3V66 edge[10]
500
ps
t6_66
CPU, 3V66
CPU-3V66 Clock Skew
CPU leads[10]
7.0
8.0
ns
t6_100
CPU, 3V66
CPU-3V66 Clock Skew
Coincident every other 3V66 edge[10]
500
ps
t7_66
CPU, SDRAM
CPU-SDRAM Clock Skew
SDRAM leads[10, 12]
2.0
3.0
ns
t7_100
CPU, SDRAM
CPU-SDRAM Clock Skew
CPU leads, measured every edge[10]
4.5
5.5
ns
t8
CPU
Cycle-Cycle Clock Jitter
Measured at 1.25V, t8A – t8B
250
ps
t8
SDRAM
Cycle-Cycle Clock Jitter
Measured at 1.5V, t8A – t8B
250
ps
t8
APIC
Cycle-Cycle Clock Jitter
Measured at 1.25V, t8A – t8B
500
ps
t8
USB
Cycle-Cycle Clock Jitter
Measured at 1.5V, t8A – t8B
500
ps
t8
3V66
Cycle-Cycle Clock Jitter
Measured at 1.5V, t8A – t8B
500
ps
t8
REF
Cycle-Cycle Clock Jitter
Measured at 1.5V, t8A – t8B
1000
ps
tSTABLE
All Outputs
Settle Time
All clock stabilization from power-up
3
ms
Notes:
8.
All parameters specified with loaded outputs as follows: CPU, APIC, REF, USB = 12.5 pF: SDRAM, 3V66, PCI=20 pF.
9.
Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V.
10. Measured at 1.25V for 2.5V clocks and 1.5V for 3.3V clocks.
11. Coincident every other APIC edge if APIC running at 16 MHz.
12. Measured every third CPU edge.
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