HD64F2145 datasheet(38/829 Pages) RENESAS

38 / 829 page

Rev. 2.0, 08/02, page xxxvi of xxxviii

Table 16.10

Permissible SCL Rise Time (t

sr) Values ................................................................455

Table 16.11

2C Bus Timing (with Maximum Influence of t

Sr/tSf) .............................................457

Section 17 Keyboard Buffer Controller

Table 17.1

Pin Configuration ..................................................................................................466

Section 18 Host Interface X-Bus Interface (XBS)

Table 18.1

Pin Configuration ..................................................................................................48 5

Table 18.2

Set/Clear Timing for STR Flags............................................................................493

Table 18.3

Host Interface Channel Selection and Pin Operation ............................................494

Table 18.4

Host Interface Operations from HIF Host, and Slave Operation...........................495

Table 18.5

GA20 (P81) Set/Clear Timing...............................................................................496

Table 18.6

Fast A20 Gate Output Signal.................................................................................497

Table 18.7

Scope of HIF Pin Shutdown..................................................................................498

Table 18.8

Input Buffer Full Interrupts ...................................................................................499

Table 18.9

HIRQ Setting/Clearing Conditions .......................................................................500

Section 19 Host Interface LPC Interface (LPC)

Table 19.1

Pin Configuration ..................................................................................................505

Table 19.2

Table 19.3

GA20 (P81) Set/Clear Timing...............................................................................539

Table 19.4

Fast A20 Gate Output Signals ..............................................................................541

Table 19.5

Scope of Host Interface Pin Shutdown..................................................................543

Table 19.6

Scope of Initialization in Each Host Interface Mode ............................................544

Table 19.7

Receive Complete Interrupts and Error Interrupt ..................................................548

Table 19.8

HIRQ Setting and Clearing Conditions.................................................................550

Section 20 D/A Converter

Table 20.1

Pin Configuration ..................................................................................................554

Table 20.2

D/A Channel Enable..............................................................................................555

Section 21 A/D Converter

Table 21.1

Pin Configuration ..................................................................................................561

Table 21.2

Analog Input Channels and Corresponding ADDR Registers...............................562

Table 21.3

A/D Conversion Time (Single Mode) ...................................................................569

Section 23 ROM

Table 23.1

Differences between Boot Mode and User Program Mode...................................579

Table 23.2

Pin Configuration ..................................................................................................585

Table 23.3

Operating Modes and ROM ..................................................................................591

Table 23.4

On-Board Programming Mode Settings................................................................591

Table 23.5

Boot Mode Operation............................................................................................594

Table 23.6

System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate

is Possible..............................................................................................................595

Section 25 Clock Pulse Generator

Table 25.1

Damping Resistance Values ..................................................................................610

HD64F2145 Datasheet(PDF) 38 Page - Renesas Technology Corp

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