HD64F2145 datasheet(15/829 Pages) RENESAS

15 / 829 page

Rev. 2.0, 08/02, page xiii of xxxviii

9.5.1

Module Stop Mode Setting...................................................................................226

Section 10 14-Bit PWM Timer (PWMX)..........................................................227

10.1

Features .............................................................................................................................227

10.2

Input/Output Pins ..............................................................................................................228

10.3

Register Descriptions.........................................................................................................228

10.3.1 PWM (D/A) Counters H and L (DACNTH, DACNTL) ......................................228

10.3.2 PWM (D/A) Data Registers A and B (DADRA, DADRB)..................................230

10.3.3 PWM (D/A) Control Register (DACR)................................................................232

10.4

Bus Master Interface .........................................................................................................233

10.5

Operation ...........................................................................................................................234

10.6

Usage Note ........................................................................................................................240

10.6.1 Module Stop Mode Setting...................................................................................240

Section 11 16-Bit Free-Running Timer (FRT) ..................................................241

11.1

Features .............................................................................................................................241

11.2

Input/Output Pins ..............................................................................................................243

11.3

Register Descriptions.........................................................................................................243

11.3.1 Free-Running Counter (FRC)...............................................................................244

11.3.2 Output Compare Registers A and B (OCRA, OCRB)..........................................244

11.3.3 Input Capture Registers A to D (ICRA to ICRD).................................................244

11.3.4 Output Compare Registers AR and AF (OCRAR, OCRAF)................................245

11.3.5 Output Compare Register DM (OCRDM) ...........................................................245

11.3.6 Timer Interrupt Enable Register (TIER) ..............................................................246

11.3.7 Timer Control/Status Register (TCSR) ................................................................247

11.3.8 Timer Control Register (TCR) .............................................................................250

11.3.9 Timer Output Compare Control Register (TOCR)...............................................251

11.4

Operation ...........................................................................................................................253

11.4.1 Pulse Output .........................................................................................................253

11.5

Operation Timing ..............................................................................................................253

11.5.1 FRC Increment Timing ........................................................................................253

11.5.2 Output Compare Output Timing ..........................................................................254

11.5.3 FRC Clear Timing ................................................................................................255

11.5.4 Input Capture Input Timing..................................................................................255

11.5.5 Buffered Input Capture Input Timing...................................................................256

11.5.6 Timing of Input Capture Flag (ICF) Setting.........................................................257

11.5.7 Timing of Output Compare Flag (OCF) setting ...................................................258

11.5.8 Timing of FRC Overflow Flag Setting.................................................................258

11.5.9 Automatic Addition Timing .................................................................................259

11.5.10 Mask Signal Generation Timing ..........................................................................259

11.6

Interrupt Sources ...............................................................................................................260

11.7

Usage Notes.......................................................................................................................261

11.7.1 Conflict between FRC Write and Clear................................................................261

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