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STR720 Datasheet(PDF) 211 Page - STMicroelectronics |
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STR720 Datasheet(HTML) 211 Page - STMicroelectronics |
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211 / 401 page  STR720 - CONTROLLER AREA NETWORK (CAN) 211/401 CAN Control Register (CAN_CR) Address Offset: 00h Reset value: 0001h 15 14 13 12 11 10 98 765 4 3210 Reserved res IE Init rw rw rw rw rw rw rw Bits 15:8 Reserved These are reserved bits. These bits are always read as ‘0’ and must always be written with ‘0’. Bit 7 Test: Test Mode Enable 0: Normal Operation. 1: Test Mode. Bit 6 CCE: Configuration Change Enable 0: No write access to the Bit Timing Register. 1: Write access to the Bit Timing Register allowed (while bit Init=1). Bit 5 DAR: Disable Automatic Re-transmission 0: Automatic Retransmission of disturbed messages enabled. 1: Automatic Retransmission disabled. Bit 4 Reserved This is a reserved bit. This bit is always read as ‘0’ and must always be written with ‘0’. Bit 3 EIE: Error Interrupt Enable 0: Disabled - No Error Status Interrupt will be generated. 1: Enabled - A change in the bits BOff or EWarn in the Status Register will generate an interrupt. Bit 2 SIE: Status Change Interrupt Enable 0: Disabled - No Status Change Interrupt will be generated. 1: Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected. 1 |
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