56F8167 datasheet(108/184 Pages) FREESCALE

108 / 184 page

56F8367 Technical Data, Rev. 7.0

108

Freescale Semiconductor

Preliminary

5.6.30.3

Vector Number - Vector Address Bus (VAB)—Bits 12–6

This read-only field shows the vector number (VAB[7:1]) used at the time the last IRQ was taken. This

field is only updated when the 56800E core jumps to a new interrupt service routine.

Note:

Nested interrupts may cause this field to be updated before the original interrupt service routine can

read it.

5.6.30.4

Interrupt Disable (INT_DIS)—Bit 5

This bit allows all interrupts to be disabled.

•

0 = Normal operation (default)

•

1 = All interrupts disabled

5.6.30.5

Reserved—Bit 4

This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.

5.6.30.6

IRQB State Pin (IRQB STATE)—Bit 3

This read-only bit reflects the state of the external IRQB pin.

5.6.30.7

IRQA State Pin (IRQA STATE)—Bit 2

This read-only bit reflects the state of the external IRQA pin.

5.6.30.8

IRQB Edge Pin (IRQB Edg)—Bit 1

This bit controls whether the external IRQB interrupt is edge- or level-sensitive. During Stop and Wait

modes, it is automatically level-sensitive.

•0 = IRQB interrupt is a low-level sensitive (default)

•1 = IRQB interrupt is falling-edge sensitive

5.6.30.9

IRQA Edge Pin (IRQA Edg)—Bit 0

This bit controls whether the external IRQA interrupt is edge- or level-sensitive. During Stop and Wait

modes, it is automatically level-sensitive.

•0 = IRQA interrupt is a low-level sensitive (default)

•1 = IRQA interrupt is falling-edge sensitive

5.6.31

Reserved—Base + $1E

5.6.32

Interrupt Priority Register 10 (IPR10)

Note: This register is NOT available in the 56F8167 device.

Base + $1F

Read

FLEXCAN2_

MSGBUF IPL

FLEXCAN2_

WKUP IPL

FLEXCAN2_

ERR IPL

FLEXCAN2_

BOFF IPL

Write

RESET

0000

56F8167 Datasheet(PDF) 108 Page - Freescale Semiconductor, Inc

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