56F8167 datasheet(147/184 Pages) FREESCALE

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External Clock Operation Timing

56F8367 Technical Data, Rev. 7.0

Freescale Semiconductor

147

Preliminary

10.5 External Clock Operation Timing

Figure 10-3 External Clock Timing

10.6 Phase Locked Loop Timing

Table 10-13 External Clock Operation Timing Requirements1

1. Parameters listed are guaranteed by design.

Characteristic

Symbol

Min

Typ

Max

Unit

Frequency of operation (external clock driver)2

2. See Figure 10-3 for details on using the recommended connection of an external clock driver.

fosc

0—

120

MHz

Clock Pulse Width3

3. The high or low pulse width must be no smaller than 8.0ns or the chip will not function.

tPW

3.0

—

External clock input rise time4

4. External clock input rise time is measured from 10% to 90%.

trise

—

External clock input fall time5

5. External clock input fall time is measured from 90% to 10%.

tfall

—

Table 10-14 PLL Timing

Characteristic

Symbol

Min

Typ

Max

Unit

External reference crystal frequency for the PLL1

1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work

correctly. The PLL is optimized for 8MHz input crystal.

fosc

8.4

MHz

PLL output frequency2 (fOUT)

2. ZCLK may not exceed 60MHz. For additional information on ZCLK and (fOUT/2), please refer to the OCCS chapter in

the 56F8300 Peripheral User Manual.

fop

160

—

260

MHz

PLL stabilization time3 -40

° to +125°C

3. This is the minimum time required after the PLL set up is changed to ensure reliable operation.

tplls

—1

External

Clock

VIH

VIL

Note: The midpoint is VIL + (VIH – VIL)/2.

90%

50%

10%

90%

50%

10%

tPW

tfall

trise

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