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STLC1510

Host Processor Interface Timing

7.2.2 GPIO Interface Timing

The GPIO[7:0] pins are memory mapped program-

mable pins. These pins can be programmed as input

or output providing visibility to internal chip access

points, as well as an ability to latch external control

signals. A special mode can be configured where the

LAMBA Bus Clock is made available on a configured

output pin GPIO[0]. For timing characterization, this

mode should be used to exercise the GPIO[7:1] pins

as both inputs and outputs. The diagram below refers

to this special mode.

Figure 17. Host Processor Interface Timing (TTL)

Table 17. Host Processor Interface Timing

Pin Name

Parameter

Min.

Max.

Reference Pin

HPI_Addr[2:0]

tse

2.45ns

w.r.t. rising HPI_BS

HPI_Addr[2:0]

tho

0.01ns

w.r.t. rising HPI_BS

HPI_CSN

tse

3.1ns

w.r.t. rising HPI_BS

HPI_CSN

tho

0.01ns

w.r.t. rising HPI_BS

HPI_RWN

tse

0.84ns

w.r.t. rising HPI_BS

HPI_RWN

tho

0.01ns

w.r.t. rising HPI_BS

HPI_Data[7:0]

tse

2.15ns

w.r.t. rising HPI_BS

HPI_Data[7:0]

tho

0.01ns

w.r.t. falling HPI_CSN

HPI_Data[7:0]

tacc

10ns

w.r.t. falling HPI_CSN

HP I _ B S

ts e

th o

HP I_ A d d r [ 2 :0 ]

H P I_ D a ta [7 :0 ]

ta cc

HP I _ R W N , H P I_ C S N

H P I _ D a ta [ 7 :0 ]

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