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SAFC161PI Datasheet(PDF) 57 Page - Infineon Technologies AG |
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SAFC161PI Datasheet(HTML) 57 Page - Infineon Technologies AG |
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57 / 400 page  &3, 7KH &HQWUDO 3URFHVVLQJ 8QLW &38 User’s Manual 4-9 1999-08 • External Memory Access Sequences The effect described here will only become noticeable, when watching the external memory access sequences on the external bus (e.g. by means of a Logic Analyzer). Different pipeline stages can simultaneously put a request on the External Bus Controller (EBC). The sequence of instructions processed by the CPU may diverge from the sequence of the corresponding external memory accesses performed by the EBC, due to the predefined priority of external memory accesses: 1st Write Data 2nd Fetch Code 3rd Read Data. • Initialization of Port Pins Modifications of the direction of port pins (input or output) become effective only after the instruction following the modifying instruction. As bit instructions (BSET, BCLR) use internal read-modify-write sequences accessing the whole port, instructions modifying the port direction should be followed by an instruction that does not access the same port (see example below). PORT_INIT_WRONG: BSET DP3.13 ;change direction of P3.13 to output BSET P3.9 ;P3.13 is still input, ;rd-mod-wr reads pin P3.13 PORT_INIT_RIGHT: BSET DP3.13 ;change direction of P3.13 to output NOP ;any instruction not accessing port 3 BSET P3.9 ;P3.13 is now output, ;rd-mod-wr reads P3.13’s output latch • Changing the System Configuration The instruction following an instruction that changes the system configuration via register SYSCON (e.g. the mapping of the internal ROM, segmentation, stack size) cannot use the new resources (e.g. ROM or stack). In these cases an instruction that does not access these resources should be inserted. Code accesses to the new ROM area are only possible after an absolute branch to this area. Note: As a rule, instructions that change ROM mapping should be executed from internal RAM or external memory. |
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