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SAFC161PI Datasheet(PDF) 80 Page - Infineon Technologies AG |
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SAFC161PI Datasheet(HTML) 80 Page - Infineon Technologies AG |
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80 / 400 page  &3, 7KH &HQWUDO 3URFHVVLQJ 8QLW &38 User’s Manual 4-32 1999-08 The Multiply/Divide Low Register MDL This register is a part of the 32-bit multiply/divide register, which is implicitly used by the CPU, when it performs a multiplication or a division. After a multiplication, this non-bit addressable register represents the low order 16 bits of the 32-bit result. For long divisions, the MDL register must be loaded with the low order 16 bits of the 32-bit dividend before the division is started. After any division, register MDL represents the 16- bit quotient. Whenever this register is updated via software, the Multiply/Divide Register In Use (MDRIU) flag in the Multiply/Divide Control register (MDC) is set to ’1’. The MDRIU flag is cleared, whenever the MDL register is read via software. When a multiplication or division is interrupted before its completion and when a new multiply or divide operation is to be performed within the interrupt service routine, register MDL must be saved along with registers MDH and MDC to avoid erroneous results. A detailed description of how to use the MDL register for programming multiply and divide algorithms can be found in chapter “System Programming”. MDL Multiply/Divide Low Reg. SFR (FE0E H/07H) Reset value: 0000 H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mdl rwh Bit Function mdl Specifies the low order 16 bits of the 32-bit multiply and divide reg. MD. |
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