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SAFC161PI Datasheet(PDF) 95 Page - Infineon Technologies AG |
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SAFC161PI Datasheet(HTML) 95 Page - Infineon Technologies AG |
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95 / 400 page  &3, ,QWHUUXSW DQG 7UDS )XQFWLRQV User’s Manual 5-13 1999-08 Continuous transfers are selected by the value FF H in bit field COUNT. In this case COUNT is not modified and the respective PEC channel services any request until it is disabled again. When COUNT is decremented from 01 H to 00H after a transfer, the request flag is not cleared, which generates another request from the same source. When COUNT already contains the value 00 H, the respective PEC channel remains idle and the associated interrupt service routine is activated instead. This allows to choose, if a level 15 or 14 request is to be serviced by the PEC or by the interrupt service routine. Note: PEC transfers are only executed, if their priority level is higher than the CPU level, i.e. only PEC channels 7...4 are processed, while the CPU executes on level 14. All interrupt request sources that are enabled and programmed for PEC service should use different channels. Otherwise only one transfer will be performed for all simultaneous requests. When COUNT is decremented to 00 H, and the CPU is to be interrupted, an incorrect interrupt vector will be generated. The source and destination pointers specifiy the locations between which the data is to be moved. A pair of pointers (SRCPx and DSTPx) is associated with each of the 8 PEC channels. These pointers do not reside in specific SFRs, but are mapped into the internal RAM of the C161PI just below the bit-addressable area (see figure below). Figure 5-2 Mapping of PEC Pointers into the Internal RAM DSTP7 00’FCFE H SRCP7 00’FCFC H DSTP6 00’FCFA H SRCP6 00’FCF8 H DSTP5 00’FCF6 H SRCP5 00’FCF4 H DSTP4 00’FCF2 H SRCP4 00’FCF0 H DSTP3 00’FCEE H SRCP3 00’FCEC H DSTP2 00’FCEA H SRCP2 00’FCE8 H DSTP1 00’FCE6 H SRCP1 00’FCE4 H DSTP0 00’FCE2 H SRCP0 00’FCE0 H |
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