ST92195D datasheet(163/249 Pages) STMICROELECTRONICS

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ST92195C/D - TELETEXT SLICER AND ACQUISITION UNIT

TELETEXT SLICER AND ACQUISITION UNIT (Cont’d)

The ACQAD1R, ACQAD0R registers are 2 read/

write registers that define the current address val-

ue, in 13 bits as follows:

ACQUISITION

ADDRESS

(ACQAD1R)

R242 - Read/Write

Reset value : 000x xxxx (xxh)

Bits 7:5 = Reserved bits. They must be left at their

reset value.

Bits 4:0 = AD[12:8]: The register content is the ad-

dress of the next free location in TDSRAM. The

address is automatically incremented by hard-

ware. It could be modified by software after each

VBI.

ACQUISITION

ADDRESS

(ACQAD0R)

R243 - Read/Write

Reset value: xxxx xxxx (xxh)

Bits 7:0 = AD[7:0]: The register content is the ad-

dress of the next free location in TDSRAM. The

address is automatically incremented by hard-

ware. It could be modified by software after each

VBI.

TELETEXT SLICER CONTROL REGISTER

(TXSCR)

R248 - Read/Write

Reset value: 0000 0110 (06h)

Bit 7 = TXTEN:

Teletext slicer enable.

0: Disables the Teletext Slicer; all analog functions

are in zero power consumption (reset state).

1: Starts the Slicer function.

Bit 6 = TXTES:

Teletext extended search.

0: Run-in Clock search starts from line 6 or 318.

1: Run-in Clock search starts at line 2 (first field)

and line 315 (second field).

Bits 5:4 = TXTGC: Teletext Pre-amplifier Gain

Control bits. These two bits control the effective

gain of the pre-amplifier stage inserted between

the CVBS1 signal input and the Teletext Slicer

comparator input. (Refer to the ADSEL bit in the

PASR register)

Bit 3 = Reserved (read only).

Bits 2:0 = Reserved bits, keep in reset state.

AD12

AD11

AD10

AD9

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

TXTEN TXTES

TXTGC

-1

TXTGC1

TXTGC0

Pre-amplifier Gain Value

1.2

2.0

3.0

3.8

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