ST92195D datasheet(166/249 Pages) STMICROELECTRONICS

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ST92195C/D - VPS & WSS SLICER

VPS & WSS SLICER (Cont’d)

7.8.2 General Operation

The VPS/WSS Slicer implements the following

features:

Wide Screen Signalling (WSS) follows the pro-

posed ETSI standard providing advanced televi-

sion features such as aspect ratio and format us-

ing 14 Bits of information extracted from Half Line

23, Field 1.

Video Programming System (VPS) follows the in-

dustry standard for VPS using 5 bytes of informa-

tion extracted from Line 16, on Field 1 (bytes 5, 11

to 14).

The input signals are treated internally by the sys-

tem as follows:

– Data: the serial data from the analog video input

is converted to serial digital data for digital

processing.

– WSS window/VPS window. For the VPS signal

treatment, the analog video signal is taken from

the CVBS1 pin after its amplification through the

programmable amplifier. For the WSS signal

treatment, the video signal is taken from the

CVBS2 pin directly. The CVBS2 pin is AC driven

through a 150pF capacitor.

– VSync: The system also receives the sync sig-

nals from the video input pin. This signal con-

tains the information telling exactly which line

and field is being processed. This is performed

in the Sync Extractor Cell with its outputs deliv-

ered to the VPS/WSS cell.

7.8.2.1 Analog Input stage

The data slicer determines the average amplitude

of the input data stream and references a compa-

rator at this value. The average amplitude is ac-

complished by AC coupling the video input signal

into the slicer cell and gating the bias circuits dur-

ing the active bi-phase signal.

7.8.2.2 Video Input Specification

The composite video baseband signal (CVBS) in-

put is 1 VPP +/- 6dB from the bottom of sync to

100IRE video for both CVBS1 (VPS path) and

CVBS2 (WSS path). The polarity of the video is

negative going sync.

7.8.2.3 Digital Decoder

The digital decoder uses the 5MHz clock as the

main timing reference and the digital outputs from

the sync and data slicer as the signal inputs. The

data for both VPS and WSS are transmitted with a

reference of 5 MHz clock with the same phase.

The serial digital data coming out of the data slicer

is first sampled at 5 MHz, this oversamples the

2.5Mbits/sec enough to process the signal under

normal conditions. The samples are then digitally

processed.

The bi-phase code is checked on both sides of the

signal with respect to a timing delay to detect er-

rors.

7.8.2.4 Framing Code and Data Check

If the framing code is recognized, the data is fur-

ther processed and a flag is set.

The data is then processed for biphase errors. If

the data is not defective, bits ERB1..5 remain at 0

and the data is stored. If the data is in error, bits

ERB1..5 are set by hardware. These bits must be

cleared by the user before the next framing code.

If a framing code is not recognized, the data is not

stored , the flag remains at 0 (VFRMVPS bit in the

VPSSR register) and the slicer waits for the next

VPS/WSS window.

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