ST92195D datasheet(164/249 Pages) STMICROELECTRONICS

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ST92195C/D - TELETEXT SLICER AND ACQUISITION UNIT

TELETEXT SLICER AND ACQUISITION UNIT (Cont’d)

TELETEXT SLICER INITIALIZATION REGISTER

(TXSLIR)

R249 - Read/Write

Reset Value: 0000 1011 (0Bh)

Bits 7:6 = Reserved bits. Keep in reset state.

Bit 5:0 = INI(5:0): 6-bit initialization value of the

Slicer DAC. This value is used to re-initialize the

Slicer DAC at each beginning of TV line.

PRE-AMPLIFIER AND ADC SELECT REGISTER

(PASR)

R255 - Read/Write

Reset Value: 0000 0000 (00h)

Bits 7:3 = Reserved bits, keep in reset state.

Bit 2 = PREAMP:

Preamplifier enable.

This bit is set and cleared by software to define the

analog CVBS input configuration of the Teletext

slicer.

0: Activate on-chip pre-amplifier providing to the

Teletext front-end Slicer an amplified CVBS sig-

nal, the gain being defined by the TXTGC(1:0)

bits of the Teletext Slicer Control Register (TX-

SCR).

1: Pre-amplifier is by-passed.

Bit 1 = Reserved bit, keep in reset state.

Bit 0 = ADCSEL:

ADC Selection.

This bit is set and cleared by software to choose

which analog signal is sent to the A/D converter

channel 0.

0: Channel 0 is connected to the VDETB signal

(amplitude of the sync pulses extracted from the

CVBS signal).

1: Channel 0 is connected to the VBGP signal (on-

chip analog reference voltage).

The Sync pulse amplitude seen at the CVBS1 pin

can be easily determined calculating the differ-

ence of 2 A/D conversions, converting first the

VDETB signal and then the VBGP signal (the max-

imum code FFh represents a 1V amplitude).

VsyncAmp= (NVDETB-NVBGP)/FF Volt

For an ideal composite video signal, the theoreti-

cal gain to program with the TXTGC(1:0) bits is:

Gth= 0.4 / VsyncAmp (V)

INI5

INI4

INI3

INI2

INI1

INI0

PRE-

AMP

ADC-

SEL

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