AT90LS8535-4AI datasheet(40/127 Pages) ATMEL

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AT90S/LS8535

1041H–11/01

OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or

OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a

full 16-bit register write operation.

The TEMP register is also used when accessing TCNT1 and ICR1. If the main program

and interrupt routines perform access to registers using TEMP, interrupts must be dis-

abled during access from the main program.

Timer/Counter1 Input Capture

The Input Capture Register is a 16-bit read-only register.

When the rising or falling edge (according to the input capture edge setting [ICES1]) of

the signal at the input capture pin (ICP) is detected, the current value of the

Timer/Counter1 is transferred to the Input Capture Register (ICR1). At the same time,

the input capture flag (ICF1) is set (one).

Since the Input Capture Register (ICR1) is a 16-bit register, a temporary register

(TEMP) is used when ICR1 is read to ensure that both bytes are read simultaneously.

When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of

the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in

the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently,

the low-byte ICR1L must be accessed first for a full 16-bit register read operation.

The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the

main program and interrupt routines perform access to registers using TEMP, interrupts

must be disabled during access from the main program.

Timer/Counter1 In PWM Mode

When the PWM mode is selected, Timer/Counter1, the Output Compare Register1A

(OCR1A) and the Output Compare Register1B (OCR1B) form a dual 8-, 9- or 10-bit,

free-running, glitch-free and phase-correct PWM with outputs on the PD5(OC1A) and

PD4(OC1B) pins. Timer/Counter1 acts as an up/down counter, counting up from $0000

to TOP (see Table 14), where it turns and counts down again to zero before the cycle is

repeated. When the counter value matches the contents of the 10 least significant bits of

OCR1A or OCR1B, the PD5(OC1A)/PD4(OC1B) pins are set or cleared according to

the settings of the COM1A1/COM1A0 or COM1B1/COM1B0 bits in the Timer/Counter1

Control Register (TCCR1A). Refer to Table 15 for details.

Note that if the Compare Register contains the TOP value and the prescaler is not in

use (CS12..CS10 = 001), the PWM output will not produce any pulse at all, because the

Bit

151413

1110

$27 ($47)

MSB

ICR1H

$26 ($46)

LSB

ICR1L

765

4321

Read/Write

RRR

Initial Value

000

0000

000

0000

Table 14. Timer TOP Values and PWM Frequency

PWM Resolution

Timer TOP value

Frequency

8-bit

$00FF (255)

TCK1/510

9-bit

$01FF (511)

fTCK1/1022

10-bit

$03FF(1023)

TCK1/2046

AT90LS8535-4AI Datasheet(PDF) 40 Page - ATMEL Corporation

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