845GL datasheet(72/193 Pages) INTEL

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Intel® 82845G/82845GL/82845GV GMCH Datasheet

3.5.1.30

AMTT—AGP MTT Control Register (Device 0)

Address Offset:

BCh

Default Value:

10h

Access:

Read Only, Read/Write

Size:

8 bits

AMTT is an 8-bit register that controls the amount of time that the GMCH’s arbiter allows AGP/

PCI master to perform multiple back-to-back transactions. The GMCH’s AMTT mechanism is

used to optimize the performance of the AGP master (using PCI semantics) that performs multiple

back-to-back transactions to fragmented memory ranges (and as a consequence it can not use long

burst transfers). The AMTT mechanism applies to the host-AGP/PCI transactions as well and it

assures the processor of a fair share of the AGP/PCI interface bandwidth.

The number of clocks programmed in the AMTT represents the guaranteed time slice (measured in

66 MHz clocks) allotted to the current agent (either AGP/PCI master or Host bridge) after which

the AGP arbiter will grant the bus to another agent. The default value of AMTT is 00h and disables

this function. The AMTT value can be programmed with 8 clock granularity. For example, if the

AMTT is programmed to 18h, then the selected value corresponds to the time period of 24 AGP

(66 MHz) clocks.

3.5.1.31

LPTT—AGP Low Priority Transaction Timer Register (Device 0)

Address Offset:

BDh

Default Value:

10h

Access:

R/W

Size:

8 bits

LPTT is an 8-bit register similar in function to AMTT. This register is used to control the minimum

tenure on the AGP for low priority data transaction (both reads and writes) issued using PIPE# or

SB mechanisms.

The number of clocks programmed in the LPTT represents the guaranteed time slice (measured in

66 MHz clocks) allotted to the current low priority AGP transaction data transfer state. This does

not necessarily apply to a single transaction but it can span over multiple low-priority transactions

of the same type. After this time expires the AGP arbiter may grant the bus to another agent if there

is a pending request. The LPTT does not apply in the case of high-priority request where ownership

is transferred directly to high-priority requesting queue. The default value of LPTT is 00h and

disables this function. The LPTT value can be programmed with 8-clock granularity. For example,

if the LPTT is programmed to 10h, then the selected value corresponds to the time period of

16 AGP (66 MHz) clocks.

Bit

Description

7:3

Multi-Transaction Timer Count Value (MTTC).

The number programmed into these bits represents

the time slice (measured in eight, 66 MHz clock granularity) allotted to the current agent (either AGP/

PCI master or GMCH bridge) after which the AGP arbiter will grant the bus to another agent.

2:0

Reserved.

Bit

Description

7:3

Low Priority Transaction Timer Count Value (LPTTC).

The number of clocks programmed in

these bits represents the time slice (measured in eight, 66 MHz clock granularity) allotted to the

current low priority AGP transaction data transfer state).

2:0

Reserved.

845GL Datasheet(PDF) 72 Page - Intel Corporation

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