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845GL Datasheet(PDF) 76 Page - Intel Corporation |
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845GL Datasheet(HTML) 76 Page - Intel Corporation |
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76 / 193 page  Register Description 76 Intel® 82845G/82845GL/82845GV GMCH Datasheet 3.5.1.35 SMICMD—SMI Command Register (Device 0) Address Offset: CC–CDh Default Value: 0000h Access: RO, R/W Size: 16 bits This register enables various errors to generate a SMI message via the hub interface. 3.5.1.36 SCICMD—SCI Command Register (Device 0) Address Offset: CE–CDh Default Value: 0000h Access: RO, R/W Size: 16 bits This register enables various errors to generate a SMI message via the hub interface. 3.5.1.37 SKPD—Scratchpad Data Register (Device 0) Address Offset: DEh Default Value: 0000h Access: R/W Size: 16 bits Bit Description 15:0 Intel Reserved. Bit Description 15:0 Intel Reserved. Bit Description 15:0 Scratchpad (SCRTCH). These bits are simply R/W storage bits that have no effect on the GMCH functionality. |
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