845GL datasheet(91/193 Pages) INTEL

Part #	845GL

Description	Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)

PDF	193 Pages

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Manufacturer	INTEL [Intel Corporation]

Direct Link	http://www.intel.com

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Intel® 82845G/82845GL/82845GV GMCH Datasheet

The bit field definitions for VGAEN and MDAP are detailed in Table 3-4.

3.5.2.22

ERRCMD1—Error Command Register (Device 1)

Address Offset:

40h

Default Value:

00h

Access:

R/W

Size:

8 bits

Table 3-4. VGAEN and MDAP Bit Definitions

VGAEN

MDAP

Description

All References to MDA and VGA space are routed to hub interface.

Illegal combination

All VGA references are routed to this bus. MDA references are routed to the hub

interface.

All VGA references are routed to this bus. MDA references are routed to hub interface.

Bit

Description

7:1

Reserved.

SERR on Receiving Target Abort (SERTA).

SERR messaging for Device 1 is globally enabled in

the PCICMD1 register.

0 = Disable. The GMCH does not assert an SERR message upon receipt of a target abort on

PCI_B.

1 = Enable. The GMCH generates an SERR message over the hub interface upon receiving a

target abort on PCI_B.

845GL Datasheet(PDF) 91 Page - Intel Corporation