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ATXMEGA32E5 Datasheet(PDF) 21 Page - Microchip Technology |
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ATXMEGA32E5 Datasheet(HTML) 21 Page - Microchip Technology |
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21 / 153 page  2018 Microchip Technology Inc. Data Sheet Complete DS40002059A-page 21 ATxmega32E5/16E5/8E5 8.10 Device ID and Revision Each device has a three-byte device ID. This ID identifies the manufacturer of the device and the device type. A separate register contains the revision number of the device. 8.11 I/O Memory Protection Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to lock the I/O register related to the clock system, the event system, and the waveform extensions. As long as the lock is enabled, all related I/O registers are locked and they cannot be written from the application software. The lock registers themselves are protected by the configuration change protection mechanism. 8.12 Flash and EEPROM Page Size The flash program memory and EEPROM data memory are organized in pages. The pages are word accessible for the flash and byte accessible for the EEPROM. Table 8-2 shows the Flash Program Memory organization and Program Counter (PC) size. Flash write and erase opera- tions are performed on one page at a time, while reading the Flash is done one byte at a time. For Flash access the Z- pointer (Z[m:n]) is used for addressing. The most significant bits in the address (FPAGE) give the page number and the least significant address bits (FWORD) give the word in the page. Table 8-2. Number of Words and Pages in the Flash Table 8-3 shows EEPROM memory organization for the AVR XMEGA E5 devices. EEPROM write and erase operations can be performed one page or one byte at a time, while reading the EEPROM is done one byte at a time. For EEPROM access the NVM address register (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) give the page number and the least significant address bits (E2BYTE) give the byte in the page. Table 8-3. Number of Words and Pages in the EEPROM Devices PC size Flash size Page Size FWORD FPAGE Application Boot bits bytes words Size No. of pages Size No. of pages ATxmega32E5 15 32K+4K 64 Z[6:0] Z[14:7] 32K 256 4K 32 ATxmega16E5 14 16K+4K 64 Z[6:0] Z[13:7] 16K 128 4K 32 ATxmega8E5 13 8K+2K 64 Z[6:0] Z[12:7] 8K 64 2K 16 Devices EEPROM Page Size E2BYTE E2PAGE No. of Pages Size bytes ATxmega32E5 1K 32 ADDR[4:0] ADDR[10:5] 32 ATxmega16E5 512Bytes 32 ADDR[4:0] ADDR[10:5] 16 ATxmega8E5 512Bytes 32 ADDR[4:0] ADDR[10:5] 16 |
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