ATXMEGA32E5 datasheet(68/153 Pages) MICROCHIP

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DS40002059A-page 68

ATxmega32E5/16E5/8E5

33. Peripheral Module Address Map

The address maps show the base address for each peripheral and module in XMEGA E5. For complete register description

and summary for each peripheral module, refer to the XMEGA E Manual.

Table 33-1.

Peripheral Module Address Map

Base Address

Name

Description

0x0000

GPIO

General Purpose IO Registers

0x0010

VPORT0

Virtual Port A

0x0014

VPORT1

Virtual Port C

0x0018

VPORT2

Virtual Port D

0x001C

VPORT3

Virtual Port R

0x0030

CPU

0x0040

CLK

Clock Control

0x0048

SLEEP

Sleep Controller

0x0050

OSC

Oscillator Control

0x0060

DFLLRC32M

DFLL for the 32MHz Internal Oscillator

0x0070

Power Reduction

0x0078

RST

Reset Controller

0x0080

WDT

Watch-Dog Timer

0x0090

MCU

MCU Control

0x00A0

PMIC

Programmable Multilevel Interrupt Controller

0x00B0

PORTCFG

Port Configuration

0x00D0

CRC

CRC Module

0x0100

EDMA

Enhanced DMA Controller

0x0180

EVSYS

Event System

0x01C0

NVM

Non Volatile Memory (NVM) Controller

0x0200

ADCA

Analog to Digital Converter on port A

0x0300

DACA

Digital to Analog Converter on port A

0x0380

ACA

Analog Comparator pair on port A

0x0400

RTC

Real Time Counter

0x0460

XCL

XMEGA Custom Logic Module

0x0480

TWIC

Two-Wire Interface on port C

0x0600

PORTA

Port A

0x0640

PORTC

Port C

0x0660

PORTD

Port D

0x07E0

PORTR

Port R

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