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ATXMEGA32E5 Datasheet(PDF) 98 Page - Microchip Technology |
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ATXMEGA32E5 Datasheet(HTML) 98 Page - Microchip Technology |
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98 / 153 page  2018 Microchip Technology Inc. Data Sheet Complete DS40002059A-page 98 ATxmega32E5/16E5/8E5 36.15 Two-Wire Interface Characteristics Table 36-6 on page 83 describes the requirements for devices connected to the two-wire interface (TWI) Bus. The AVR XMEGA TWI meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 36-7. Figure 36-7. Two-wire Interface Bus Timing Table 36-30. Two-wire Interface Characteristics Symbol Parameter Condition Min. Typ. Max. Units VIH Input high voltage 0.7VCC VCC+0.5 V VIL Input low voltage -0.5 0.3VCC Vhys Hysteresis of Schmitt trigger inputs 0.05VCC(1) VOL Output low voltage 3mA, sink current 0 0.4 IOL Low level output current fSCL ≤ 400kHz VOL = 0.4V 3 mA fSCL ≤ 1MHz 20 tr Rise time for both SDA and SCL fSCL ≤ 400kHz 20+0.1Cb(1)(2) 300 ns fSCL ≤ 1MHz 120 tof Output fall time from VIHmin to VILmax 10pF< Cb<400pF(2) fSCL ≤ 400kHz 20+0.1Cb(1)(2) 250 fSCL ≤ 1MHz 120 tSP Spikes suppressed by Input filter 0 50 II Input current for each I/O Pin 0.1 VCC <VI <0.9 VCC -10 10 µA CI Capacitance for each I/O Pin 10 pF fSCL SCL clock frequency fPER(3) > max(10fSCL,250kHz) 0 1 MHz RP Value of pull-up resistor fSCL ≤ 100kHz (VCC-0.4V)/ IOL 100ns/Cb Ω fSCL ≤ 400kHz 300ns/Cb fSCL ≤ 1MHz 550ns/Cb tHD;STA Hold time (repeated) START condition fSCL ≤ 100kHz 4 µs fSCL ≤ 400kHz 0.6 fSCL ≤ 1MHz 0.26 tHD;STA tof SDA SCL tLOW tHIGH tSU;STA tBUF tr tHD;DAT tSU;DAT tSU;STO |
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