STM32F722IC datasheet(140/229 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F722xx STM32F723xx

140/229

DS11853 Rev 6

6.3.12

PLL spread spectrum clock generation (SSCG) characteristics

The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic

interferences (see Table 57: EMI characteristics). It is available only on the main PLL.

Equation 1

The frequency modulation period (MODEPER) is given by the equation below:

fPLL_IN and fMod must be expressed in Hz.

As an example:

If fPLL_IN = 1 MHz, and fMOD = 1 kHz, the modulation depth (MODEPER) is given by

equation 1:

Equation 2

Equation 2 allows to calculate the increment step (INCSTEP):

fVCO_OUT must be expressed in MHz.

With a modulation depth (md) =

±2 % (4 % peak to peak), and PLLN = 240 (in MHz):

IDD(PLLSAI)(4)

PLLSAI power consumption on

VDD

VCO freq = 100 MHz

VCO freq = 432 MHz

0.15

0.45

0.40

0.75

IDDA(PLLSAI)(4)

PLLSAI power consumption on

VDDA

VCO freq = 100 MHz

VCO freq = 432 MHz

0.30

0.55

0.40

0.85

1. Take care of using the appropriate division factor M to have the specified PLL input clock values.

2. Guaranteed by design.

3. Value given with main PLL running.

4. Guaranteed by characterization results.

Table 46. PLLISAI characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Table 47. SSCG parameters constraint

Symbol

Parameter

Min

Typ

Max(1)

Unit

fMod

Modulation frequency

KHz

Peak modulation depth

0.25

MODEPER * INCSTEP

215

− 1-

1. Guaranteed by design.

MODEPER

round fPLL_IN 4fMod

()

⁄

[]

MODEPER

round 10

410

()

⁄

[]

250

INCSTEP

round

–

() md PLLN

() 100 5

MODEPER

()

⁄

[]

INCSTEP

round

–

() 2 240

() 100 5

250

()

⁄

[]

126md(quantitazed)%

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