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STM32G47PBY3XXX Datasheet(PDF) 182 Page - STMicroelectronics

Part # STM32G47PBY3XXX
Description  Arm® Cortex®-M4 32-bit MCUFPU, up to 512 KB Flash, 170 MHz / 213DMIPS, 128 KB SRAM, rich analog, math accelerator
PDF  229 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32G47PBY3XXX Datasheet(HTML) 182 Page - STMicroelectronics

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Electrical characteristics
STM32G473xB STM32G473xC STM32G473xE
182/229
DS12712 Rev 3
Table 95. Asynchronous multiplexed PSRAM/NOR write timings(1)(2)
1. CL = 30 pF.
2. Guaranteed by characterization results.
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
3 THCLK - 0.5 3 THCLK + 1
ns
tv(NWE_NE) FMC_NEx low to FMC_NWE low
THCLK - 0.5
THCLK + 1
tw(NWE)
FMC_NWE low time
THCLK - 2
THCLK + 1
th(NE_NWE) FMC_NWE high to FMC_NE high hold time
THCLK - 0.5
-
tv(A_NE)
FMC_NEx low to FMC_A valid
-
0
tv(NADV_NE) FMC_NEx low to FMC_NADV low
0
1.5
tw(NADV)
FMC_NADV low time
THCLK + 0.5
THCLK + 1.5
th(AD_NADV)
FMC_AD(address) valid hold time after
FMC_NADV high
THCLK - 3
-
th(A_NWE)
Address hold time after FMC_NWE high
Address hold
until next
write
operation
-
th(BL_NWE) FMC_BL hold time after FMC_NWE high
THCLK - 0.5
-
tv(BL_NE)
FMC_NEx low to FMC_BL valid
-
0
tv(Data_NADV) FMC_NADV high to Data valid
-
THCLK + 2
th(Data_NWE) Data hold time after FMC_NWE high
THCLK + 6
-
Table 96. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)(2)
1. CL = 30 pF.
2. Guaranteed by characterization results.
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
9 THCLK - 1
9 THCLK + 1
ns
tw(NWE)
FMC_NWE low time
6 THCLK - 1 6 THCLK + 0.5
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high
7 THCLK + 17
-
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 5 THCLK + 17
-



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