STM32G47PBY3XXX datasheet(29/229 Pages) STMICROELECTRONICS

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DS12712 Rev 3

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STM32G473xB STM32G473xC STM32G473xE

Functional overview

3.16

DMA request router (DMAMux)

When a peripheral indicates a request for DMA transfer by setting its DMA request line, the

DMA request is pending until it is served and the corresponding DMA request line is reset.

The DMA request router allows to route the DMA control lines between the peripherals and

the DMA controllers of the product.

An embedded multi-channel DMA request generator can be considered as one of such

peripherals. The routing function is ensured by a multi-channel DMA request line

multiplexer. Each channel selects a unique set of DMA control lines, unconditionally or

synchronously with events on synchronization inputs.

For simplicity, the functional description is limited to DMA request lines. The other DMA

control lines are not shown in figures or described in the text. The DMA request generator

produces DMA requests following events on DMA request trigger inputs.

3.17

Interrupts and events

3.17.1

Nested vectored interrupt controller (NVIC)

The STM32G473xB/xC/xE devices embed a nested vectored interrupt controller which is

able to manage 16 priority levels, and to handle up to 102 maskable interrupt channels plus

the 16 interrupt lines of the Cortex®-M4.

The NVIC benefits are the following:

•

Closely coupled NVIC gives low latency interrupt processing

•

Interrupt entry vector table address passed directly to the core

•

Allows early processing of interrupts

•

Processing of late arriving higher priority interrupts

•

Support for tail chaining

•

Processor state automatically saved

•

Interrupt entry restored on interrupt exit with no instruction overhead

The NVIC hardware block provides flexible interrupt management features with minimal

interrupt latency.

3.17.2

Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 44 edge detector lines used to generate

interrupt/event requests and to wake-up the system from the Stop mode. Each external line

can be independently configured to select the trigger event (rising edge, falling edge, both)

and can be masked independently.

A pending register maintains the status of the interrupt requests. The internal lines are

connected to peripherals with wakeup from Stop mode capability. The EXTI can detect an

external line with a pulse width shorter than the internal clock period. Up to 107 GPIOs can

be connected to the 16 external interrupt lines.

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