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ADRV9009-W/PCBZ Datasheet(PDF) 13 Page - Analog Devices |
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ADRV9009-W/PCBZ Datasheet(HTML) 13 Page - Analog Devices |
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13 / 127 page ![]() Data Sheet ADRV9009 Rev. B | Page 13 of 127 Parameter Symbol Min Typ Max Unit Test Conditions/Comments JESD204B DATA OUTPUT TIMING AC-coupled Unit Interval UI 81.38 320 ps Data Rate per Channel, Nonreturn to Zero (NRZ) 3125 12,288 Mbps Rise Time tR 24 39.5 ps 20% to 80% in 100 Ω load Fall Time tF 24 39.4 ps 20% to 80% in 100 Ω load Output Common-Mode Voltage VCM 0 1.8 V AC-coupled Differential Output Voltage VDIFF 360 600 770 mV Short-Circuit Current IDSHORT −100 +100 mA Differential Termination Impedance 80 94.2 120 Ω Total Jitter 15.13 ps Bit error rate (BER) = 10−15 Uncorrelated Bounded High Probability Jitter UBHPJ 0.56 ps Duty Cycle Distortion DCD 0.369 ps SYSREF_IN± Setup Time to REF_CLK_IN± 2.5 ns See Figure 2 SYSREF_IN± Hold Time to REF_CLK_IN± −1.5 ns See Figure 2 Latency tLAT_FRM REF_CLK_IN± = 245.76 MHz 116.5 Clock cycles Observation receiver bandwidth = 450 MHz, IQ rate = 491.52 MHz, lane rate = 9830.4 MHz, number of converters (M) = 4, number of lanes (L) = 2, converter resolution (N) = 16, number of samples per converter (S) = 1 237.02 ns 89.4 Clock cycles Receiver bandwidth = 200 MHz, IQ rate = 245.76 MHz, lane rate = 9830.4 MHz, M = 2, L = 2, N = 16, S = 1 364.18 ns JESD204B DATA INPUT TIMING AC-coupled Unit Interval UI 81.38 320 ps Data Rate per Channel (NRZ) 3125 12288 Mbps Differential Voltage VDIFF 125 750 mV Termination Voltage (VTT) Source Impedance ZTT 8.9 30 Ω Differential Impedance ZRDIFF 80 105.1 120 Ω Termination Voltage VTT Ω AC-Coupled 1.267 1.33 V Latency tLAT_DEFRM 74.45 Clock cycles Device clock = 245.76 MHz, transmitter bandwidth = 200 MHz, IQ rate = 491.52 MHz, lane rate = 9830.4 MHz, M = 2, L = 2, N = 16, S = 1 153.5 ns 1 VDDA1P3 refers to all analog 1.3 V supplies, including: VDDA1P3_RF_SYNTH, VDDA1P3_BB, VDDA1P3_RX_RF, VDDA1P3_RX_TX, VDDA1P3_RF_VCO_LDO, VDDA1P3_RF_LO, VDDA1P3_DES, VDDA1P3_SER, VDDA1P3_CLOCK_SYNTH, VDDA1P3_CLOCK_VCO_LDO, VDDA1P3_AUX_SYNTH, and VDDA1P3_AUX_VCO_LDO. |
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