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IMXRT1160CEC Datasheet(PDF) 19 Page - NXP Semiconductors |
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IMXRT1160CEC Datasheet(HTML) 19 Page - NXP Semiconductors |
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19 / 124 page  Modules list i.MX RT1160 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 04/2021 NXP Semiconductors 19 uSDHC1 uSDHC2 SD/MMC and SDXC Enhanced Multi-Media Card / Secure Digital Host Controller Connectivity Peripherals i.MX RT1160 specific SoC characteristics: All four MMC/SD/SDIO controllers are identical and are based on the uSDHC. They are: • Fully compliant with MMC command/response sets and Physical Layer as defined in the Multimedia Card System Specification. • Fully compliant with SD command/response sets and Physical Layer as defined in the SD Memory Card Specifications, v3.0 including high-capacity SDXC cards up to 2 TB. • Fully compliant with SDIO command/response sets and interrupt/read-wait mode as defined in the SDIO Card Specification, Part E1, v3.0 Two ports support: • 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to UHS-I SDR104 mode (104 MB/s max) • 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52 MHz in both SDR and DDR modes (104 MB/s max) • 4-bit or 8-bit transfer mode specifications for eMMC chips up to 200 MHz in HS200 mode (200 MB/s max) VIDMUX Video mux Mux control Video mux are mux control for Parallel CSI (IO PADs), MIPI CSI-2, MIPI DSI, Parallel LCDIF (IO PADs) and CSI, LCDIF-V2, eLCDIF control. It also includes the DCIC of MIPI DSI and Parallel DSI. WDOG1 WDOG2 WDOG3 WDOG4 Watch Dog Timer Peripherals WDOG1 and WDOG2 Timer support two comparison points during each counting period. Each of the comparison points is configurable to evoke an interrupt to the Arm core, and a second point evokes an external event on the WDOG line. WDOG3 and WDOG4 modules are high reliability independent timers that are available for system to use. They provide a safety feature to ensure software is executing as planned and the CPU is not stuck in an infinite loop or executing unintended code. If the WDOG module is not serviced (refreshed) within a certain period, it resets the MCU. Windowed refresh mode is supported as well. XBARA XBARB Cross BAR Cross Trigger Each crossbar switch is an array of muxes with shared inputs. Each mux output provides one output of the crossbar. The number of inputs and the number of muxes/outputs are user configurable and registers are provided to select which of the shared inputs are routed to each output. Table 3. i.MX RT1160 modules list (continued) Block Mnemonic Block Name Subsystem Brief Description |
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