FBSGAM02PR50 datasheet(6/33 Pages) EPC-CO

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FBS-GAM02-P-R50 Datasheet

Parameter

Symbol

Test Conditions

MIN

TYP

MAX

Units

Power Switch Output Capacitance

COSS

BOUT-PGND or VDD-TOUT = 5 VDC

1150

BOUT-PGND or VDD-TOUT = 50 VDC

500

Dynamic Gate/Driver Losses

(Per Driver; Low- or High-Side)

PGD

VBIAS = 5 VDC

mW/

MHz

Internal Bootstrap Capacitance

CBoot

External Bootstrap Capacitance

CBoot(ext)

TBST (Pin 10) to TOS (Pin 8)

1.0

μF

LGND-PGND Resistance

1.0

High-side Power Switch Start Up

Pre-Charge Time:

Half Bridge Configuration

tprg

(Notes 3, 10, 11, 12)

High-side Power Switch Maximum

Duty Cycle

td/c

Minimum Switching Frequency:

Low-side Power Switch

(Notes 3, 10, 11, 12, 13, 14,15,16)

Minimum Switching Frequency:

High-side Power Switch

200

kHz

Maximum Switching Frequency:

Half-Bridge Configuration

1.0

MHz

Shoot-Through Protection Activation

Delay Time

tst

(Notes 3, 14)

Module Dynamic Electrical Characteristics (T

C = 25°C unless otherwise noted)

Specification Notes

1.) VBIAS = +5 VDC, PGND = LGND = 0 VDC, VDS = VDD-to-TOUT or VDS = BOUT-to-PGND as specified.

2.) Measured using 4-Wire (Kelvin) sensing techniques and guaranteed by design.

3.) Guaranteed by design. Not tested in production.

4.) When either logic input (BIN or TIN) is at the low input voltage level the associated output (BOUT or TOUT) is guaranteed to be OFF (high

impedance).

5.) When either logic input (BIN or TIN) is at the high input voltage level the associated output (BOUT or TOUT) is guaranteed to be ON (low

impedance).

6.) Parameter measured with a 4.7 kΩ pull-up resistor between PG and VBIAS.

7.) PG is at a low level when VBIAS is below the UVLO- (falling) threshold level or the OVLO+ (rising) threshold level. PG is at a high level

when VBIAS is above the UVLO+ (rising) threshold level or the OVLO- (falling) threshold level.

8.) PG is an open drain output referenced to LGND.

9.) VBIAS levels below the UVLO- and above the OVLO+ thresholds result in the internal low-side and high-side gate drivers being

disabled: The logic inputs to the drivers are internally set to a logic low state to prevent damage to the eGaN® power switches.

10.) The high-side power switch gate driver utilizes a bootstrap capacitor to provide the proper bias for this circuit. As such, this

capacitor

MUST be periodically re-charged from the VBIAS supply. As a stand-alone high-side switch with a ground-connected/

ground-sensed load, this recharging takes place each time the switch is turned OFF and the TOUT node returns to ground potential

(0 VDC). However, when connected in conjunction with the low-side power switch in the half-bridge configuration, this connection to

ground does not exist until the low-side power switch is turned ON, thus creating a low impedance connection from TOUT through

the low-side power switch (BOUT-PGND). The time tprg is the minimum time required to ensure that the bootstrap capacitor is

properly charged when power is initially applied to the FBS-GAM02-P-R50 Module.11.) The high side gate driver utilizes a bootstrap

capacitor to provide the proper bias for this circuit. As such, this capacitor

MUST be periodically re-charged from the VBIAS supply.

The time tpcg is the minimum time required to ensure that the bootstrap capacitor is properly charged when power is initially applied

to the FBS-GAM02P-R- PSE Module.

FBSGAM02PR50 Datasheet(PDF) 6 Page - Efficient Power Conversion Corporation.

FBSGAM02PR50 Datasheet(HTML) 6 Page - Efficient Power Conversion Corporation.

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