FBSGAM02PR50 datasheet(19/33 Pages) EPC-CO

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FBS-GAM02-P-R50 Datasheet

Pin Descriptions

BIN (Pin 1)

The BIN pin is the logic input for low-side power driver. When the BIN input pin is logic low (“0”), the

low-side output (BOUT-PGND) pins (pins 13 and 14) are in the OFF (high-impedance) state. When

the BIN input pin is logic high (“1”), the BOUT-PGND pins are in the ON (low impedance) state.

TIN (Pin 2)

The TIN pin is the logic input for high-side power driver. When the TIN input pin is logic low (“0”),

the high-side output (VDD-TOUT) pins (pins 11 and 12) are in the OFF (high impedance) state. When

the TIN input pin is logic high (“1”), the VDD-TOUT pins are in the ON (low impedance) state.

LGND (Logic Ground) (Pin 3)

For proper operation of the FBS-GAM02-P-R50, the LGND pin (Pin 3) MUST be connected

directly to the system logic ground return in the application circuit.

VBIAS (Pin 4)

The VBIAS pin is the raw input DC power input for the FBS-GAM02-P-R50 module. It is

recommended that a 1.0 microfarad ceramic capacitor and a 0.1 microfarad ceramic capacitor,

each 25 VDC rating, be connected between VBIAS (pin 4) and system power ground plane (the

common tie point of PGND1 and the ground plane) to obtain the specified switching performance.

PG (Power Good) (Pin 5)

The PG pin is an open drain logic-compatible output. For proper operation the PG pin must be

pulled-up to VBIAS, external to the module, with a 4.7 kΩ resistor.

The FBS-GAM02-P-R50 incorporates a Power Good (PG) sensing circuit that disables both the low- and high-side internal gate drivers

when the +5 VDC gate drive bias potential (VBIAS) falls below an under-voltage threshold, typically 4.45 VDC, or rises above a potentially-

damaging VBIAS over-voltage threshold level – refer to Figure 5 for the proper operational nomenclature and functionality versus the state of

the VBIAS power supply. During the time when the VBIAS potential is outside of the pre-set threshold(s), the PG output (Pin 5) pin is logic low

(“0”). Alternatively, when the VBIAS potential is within the pre-set thresholds the PG pin is logic high (“1”). The logic condition of the PG pin

may be sensed by a rad hard FPGA or Microcontroller/DSP in-order to determine when the power switches in the FBS-GAM02-P-R50 may

be driven with a pulse-width modulated (PWM) input signal(s) at the BIN and TIN logic inputs. If either the under-voltage and over-voltage

indication features are not required or desired, then these functions may be disabled separately by connecting the *SD (Pin 6) pin to VBIAS

(pin 4) for the UVLO or the SD pin (Pin 7) to LGND (pin 3) for the 0 VDC indicator, as shown in Figure 17.

*SD (Pin 6)

The *SD pin is a low-true disable input for the FBS-GAM02-P-R50 module.

Both the low- and high-side power switches may be disabled (set to their high impedance OFF state) utilizing the *SD input, as shown in

Figure 19. To disable the FBS-GAM02-P-R50 module power outputs, the *SD (Pin 6) input may be driven by an open drain or open collector

that pulls this input to logic ground (LGND, pin 3). If the *SD shutdown function is not required, this pin should be left OPEN (no connection).

SD (Shutdown) (Pin 7)

The SD pin is a high-true disable input for the FBS-GAM02-P-R50 module.

Both the low- and high-side power switches may be disabled (set to their high impedance OFF state) utilizing the SD input, as shown in

Figure 20. To disable the FBS-GAM02-P-R50 module power outputs, the SD (Pin 7) input may be driven by an open drain or open collector

that pulls this input to VBIAS (pin 4). If the SD shutdown function is not required, this pin should be left OPEN (no connection).

TOS (Pin 8)

The TOS pin is the external connection to the switching node side (TOUT) of the high-side gate driver internal bootstrap capacitor.

If additional, external, bootstrap capacitance is desired, then this capacitor should be connected between TOS and TBST (pin 10).

If external bootstrap capacitance is required, then pin 8 should be left OPEN (no connection).

Top (X-Ray) View

18 Pin Molded SMT Package

with Pillar Pins

Bottom (Pad) View

FBSGAM02PR50 Datasheet(PDF) 19 Page - Efficient Power Conversion Corporation.

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