FBSGAM02PR50 datasheet(23/33 Pages) EPC-CO

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FBS-GAM02-P-R50 Datasheet

High-Side Bootstrap Capacitor Periodic Recharge

DC Operation and Power-Up Sequencing

Recommended VDD-to-PGND Power Supply Bypassing

The high-side power switch gate driver utilizes a bootstrap capacitor to provide the proper bias for this circuit during switching

operation. As such, this capacitor

MUST be periodically re-charged from the VBIAS power supply. As a stand-alone high-side switch with

a ground-connected/ground-sensed load, this recharging takes place each time the switch is turned OFF and the TOUT node returns

to ground potential (0 VDC). However, when connected in conjunction with the low-side power switch in the Half-Bridge configuration

(See Figure 10, for example), this connection to ground does not exist until the low-side power switch is turned ON, thus creating a

low impedance connection from TOUT through the low-side power switch (BOUT-PGND). If the high-side gate driver is not provided with

periodic recharge during operation, damage may occur to the Module.

The time tprg is the minimum time required for the low-side driver to be turned ON in order to ensure that the bootstrap capacitor is

properly charged when power is initially applied to the FBS-GAM02-P-R50 Module.

If DC operation is desired for the Module when connected as two single, independent, power drivers (see Figures 6, 7 or 8, for examples)

then an isolated +4.5 to +5.5 VDC power supply capable of operation with high rates-of-change of voltage from primary-to-secondary

should be connected to the TBST (pin 10) and TOS (pin 9) pins on the Module to provide DC power to the high-side gate driver.

The recommended power sequencing for the FBS-GAM02-P-R50 is the VBIAS power supply is applied first and within the recommended

operating voltage range prior to the application of VDD to the circuit.

The FBS-GAM02P-R-50 is designed as a switching eGAN® HEMT multifunction driver that is inherently capable of DC (steady-state)

operation. As such, there are precautions that must be observed during the application and operation of this Module.

One of these

precautions is power-up sequencing. The power MUST be sequenced to the circuit with VBIAS being applied first and within its

recommended operating voltage range before VDD is applied to the circuit. This will prevent the gate driver output (OUT) from

assuming a non-deterministic state with regards to the logic input (IN) and unintentionally providing an internal drive signal to

the internal eGaN® HEMT power switches. Under NO circumstances should an FBS-GAM02-P-R50 Module be used in a half-

bridge configuration with VDD applied first, prior to VBIAS, to the Module.

The power supply pins and return pin of the FBS-GAM02-P-R50 require proper high frequency bypassing to one-another in order to

prevent harmful switching noise-related spikes from degrading or damaging the internal circuitry in the FBS-GAM02-P-R50 module.

The more critical bypassing situation is related to the VDD supply to PGND (Pin 14), which bears the high rate-of-change voltages and

currents associated with the internal eGaN® power switches interacting with a load. It is recommended that a minimum of two (2) 4.7

microfarad ceramic capacitors, one (1) 1.0 microfarad ceramic capacitor and one (1) 0.1 microfarad ceramic capacitor, all with 100 VDC

ratings, be connected from VDD to PGND. All four of these capacitors should be low ESR types, if possible. It is strongly recommended

that these capacitors inscribe the smallest possible loop area between VDD and PGND so as to minimize the inductance related to

this loop area. Figure 21 illustrates three instances of recommended and acceptable VDD-PGND bypassing, as implemented in PCB

copper etch. Regardless, different end-use implementations will require different VDD bypass capacitor placements, and it is strongly

recommended that the chosen bypassing scheme be evaluated in hardware for its effectiveness.

It is also recommended that a 1.0 microfarad ceramic capacitor and a 0.1 microfarad ceramic capacitor, each 25 VDC rating, be

connected between VBIAS (pin 4) and PGND (pin 3).

FBSGAM02PR50 Datasheet(PDF) 23 Page - Efficient Power Conversion Corporation.