FBSGAM02PR50 datasheet(18/33 Pages) EPC-CO

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FBS-GAM02-P-R50 Datasheet

Adaptive Dead Time Control For the FBS-GAM02-P-R50

In circuits shown in both Figure 14 and 15 the dead times required by the FBS-GAM02-P-R50 to avoid cross-conduction/shoot-through

are generated in a “brute force” manner either with analog components (Figure 14) or with programmable logic and firmware in an

FPGA/ASIC (Figure 15). There is another way to obtain the optimum dead times for the FBS-GAM02-P-R50 device – adaptive dead time

control, as shown in Figure 16.

Adaptive dead time control utilizes the state of the switching node (SN) of the GAM02 in order to allow the BIN or TIN signals (in this

case the BIN signal is the simple logical inverse of the TIN signal) to be applied to the BIN or TIN logic inputs of the FBS-GAM02-P-R50

in order to avoid dynamic cross-conduction/shoot-though in the low- and high-side output power HEMTs. If the switching node of the

FBS-GAM02-P-R50 is “low” (i.e. at PGND) then the low-side switch is turned ON, or in the process of turning OFF, and the high-side

switch must not be turned ON (i.e. a logic 1 applied to the TIN input). Similarly, if the switching node is “high” (i.e. at VDD), then the-high

side switch is turned ON, or in the process of turning OFF, and the low-side switch must not be turned ON (i.e. a logic 1 applied to the

BIN input). However, if the BIN input is logic 0 and the switching node is “high” (i.e. the high-side catch Schottky conducting load current)

then the TIN input may be set to logic 1 to turn on the high-side driver. This same situation applies to the high-side driver: If the TIN input

is logic 0 and the switching node is “low” (i.e. the low-side catch Schottky is conducting load current) then the BIN input may be set to

logic 1 to turn on the low-side driver. The circuit shown in Figure 16 relies on a similar voltage clamping scheme for the switching node

as was utilized in Figures 14 and 15, with the exception that the power supply VDD, and subsequent range of the switching node, could

be much higher than 12 VDC – in fact up to 50 VDC for the FBS-GAM02-P-R50. So greater care must be exercised in the selection of

the clamping components to avoid excessive power dissipation in them, and the associated decrease in circuit efficiency. It is strongly

recommended to simulate the circuit once the components have been selected to ensure that the proper clamping level is achieved and

that the power dissipation of the clamp circuit is kept to a reasonable level so as not to affect overall circuit operating efficiency.

The key objective in the application of the adaptive dead time control circuit is to minimize the time delay associated with the voltage

clamping circuit. Ideally, the desired time delay of the clamping circuit is zero in order to achieve the lowest (optimum) dead times.

However, some delay is expected because the Zener diode clamp has finite capacitance and the biasing/current limiting delay resistors

contribute an R1-Czener inherent delay. There are certainly other methods to level-shift and monitor the switching node so as to ascertain

its voltage level/state. Again, the key is to determine that state as quickly as possible so that switching decisions may be made at the BIN

and TIN inputs of the FBS-GAM02-P-R50 as quickly as possible.

Figure 16. Adaptive Dead Time Control for Cross-Conduction/Shoot-Through Avoidance

TIN

BIN

PWM Signal:

From FPGA/ASIC or

PWM Controller

From GAM02

Half-Bridge

Switching Node

FBSGAM02PR50 Datasheet(PDF) 18 Page - Efficient Power Conversion Corporation.