ACE25AA128GFMLTH datasheet(48/71 Pages) ACE

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ACE25AA128G

Serial NOR Flash Memory

128 Megabits 3.0V Quad I/O Serial Flash Memory with 4KB Uniform Sector

VER 1.1

Erase Security Registers (44H)

The ACE25AA128G provides four 256-byte Security Registers which only erased all at once but able to

program individually. These registers may be used by the system manufacturers to store security and

other important information separately from the main memory array.

The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable

(WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit.

The Erase Security Registers command sequence: CS# goes low→sending Erase Security Registers

Command→CS# goes high. The command sequence is shown in Figure 35. CS# must be driven high

after the eighth bit of the command code has been latched in, otherwise the Erase Security Registers

command is not executed. As soon as CS# is driven high, the self-timed Erase Security Registers cycle

(whose duration is tSE) is initiated. While the Erase Security Registers cycle is in progress, the Status

bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is completed.

At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The

Security Registers Lock Bit (LB1,LB0) in the Status Register can be used to OTP protect the security

registers. Once the LB bit is set to 1, the Erase Security Registers will be permanently locked; the Erase

Security Registers command will be ignored.

Address

A23-A16

A15-A10

A9-A0

Security Registers

00000000

000000

Don’Care

Figure34a. The Global Block/Sector Unlock Sequence Diagram(QPI)

ACE25AA128GFMLTH Datasheet(PDF) 48 Page - ACE Technology Co., LTD.