ACE25AA128GFMLTH datasheet(12/71 Pages) ACE

12 / 71 page

ACE25AA128G

Serial NOR Flash Memory

128 Megabits 3.0V Quad I/O Serial Flash Memory with 4KB Uniform Sector

VER 1.1

QE bit.

The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad

operation. When the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE bit

is set to 1, the Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during standard

SPI or Dual SPI operation if the WP# or HOLD# pins are tied directly to the power supply or ground).

LB1,LB0, bits.

The LB1, LB0, bits are non-volatile One Time Program (OTP) bits in Status Register (S11-S10) that

provide the write protect control and status to the Security Registers. The default state of LB1-LB0 are0,

the security egisters are unlocked. The LB1-LB0 bits can be set to 1 individually using the Write Register

instruction. The LB1-LB0 bits are One Time Programmable, once its set to 1, 2 pages of Security

Registers will become read-only permanently, and the other 2 pages of Security Registers cannot be

erased.

CMP bit.

The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction with the

BP4-BP0 bits to provide more flexibility for the array protection. Please see the Status registers Memory

Protection table for details. The default setting is CMP=0.

WPS

The WPS Bit is used to select which Write Protect scheme should be used. When WPS=0, the device will

use the combination of CMP, BP (4:0) bits to protect a specific area of the memory array. When WPS=1,

the device will utilize the Individual Block Locks to protect any individual sector or blocks. The default

value for all Individual Block Lock bits is 1 upon device power on or after reset.

HOLD/RST

The HOLD/RST bit is used to determine whether HOLD# or RESET# function should be implemented on

the hardware pin for 8-pin packages. When HOLD/RST=0, the pin acts as HOLD#, When the

HOLD/RST=1, the pin acts as RESET#. However, the HOLD# or RESET# function are only available

when QE=0, If QE=1, The HOLD# and RESET# functions are disabled, the pin acts as dedicated data I/O

pin.

Commands Description

All commands, addresses and data are shifted in and out of the device, beginning with the most

significant bit on the first rising edge of SCLK after CS# is driven low. Then, the one-byte command code

must be shifted in to the device, most significant bit first on SI, each bit being latched on the rising edges

of SCLK.

ACE25AA128GFMLTH Datasheet(PDF) 12 Page - ACE Technology Co., LTD.