DS20006554A datasheet(21/94 Pages) MICROCHIP

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ZL30260-ZL30263

Data Sheet

DS20006554A

the pulse is high and the signal is low the remainder of the cycle. When POL=1, the pulse is low and the signal is

high the remainder of the cycle.

Note that duty cycle adjustment is done in the low-speed divider. Therefore when OCxCR3.LSSEL=0 the duty cycle

of the output is not affected. Also, when a CMOS output is configured with OCxCR3.LSSEL=0 and

OCxCR3.NEGLSD=1, the OCxN pin has duty cycle adjustment but the OCxP pin does not. This allows a higher-

speed 50% duty cycle clock signal to be output on the OCxP pin and a lower-speed frame/phase/time pulse (e.g.

2kHz, 8kHz or 1PPS) to be output on the OCxN pin at the same time.

An output configured for CMOS or HSTL signal format should not be configured to have a duty cycle with high time

shorter than 2ns or low time shorter than 2ns.

5.6.4

Output Phase Adjustment

The phase of an output signal can be shifted by 180

 by setting OCxCR2.POL=1. In addition, the phase can be

adjusted using the OCxPH.PHADJ register field. The adjustment is in units of bank source clock cycles. For example,

if the bank source clock is 625MHz (from the APLL for example) then one bank source clock cycle is 1.6ns, the

smallest phase adjustment is 0.8ns, and the adjustment range is ±5.6ns.

5.6.5

Output-to-Output Phase Alignment

A 0-to-1 transition of the ACR1.DALIGN bit causes a simultaneous reset of the medium-speed dividers and low-

speed dividers for all output clocks following the APLL where OCxCR1.PHEN=1. After this reset, all PHEN=1 output

clocks from the same APLL divider (IntDiv or FracDiv) are rising-edge aligned, with the phase of each output clock

signal adjusted as specified by its OCxPH.PHADJ register field. Alignment of clocks from IntDiv with clocks from

FracDiv is not supported. Similarly a 0-to-1 transition of the P2CR1.DALIGN bit aligns all output clocks following Path

2 where OCxCR1.PHEN=1. Alignment is not glitchess; i.e. it may cause a short high time or low time on participating

output clock signals. A glitchless alignment can be accomplished by first stopping the clocks, then aligning them,

then starting them. Output clock start and stop is described in section 5.6.7.

5.6.6

Output-to-Input Phase Alignment

The best approach for achieving output-to-input phase alignment is to use external feedback in which an OCx output

is connected to an ICx input. To enable external feedback, set AFBDL.EXTFB=1, set AFBDL.FBSEL to specify the

external feedback path, and provide the associated output-to-input wiring on the PCB. In this configuration the APLL,

in a closed-loop manner, automatically phase-aligns all OCx outputs from the APLL to the

APLL’s selected reference.

Any small error in this alignment due to wire delays can be compensated in the outputs’ phase adjustment registers,

OCxPH.PHADJ.

5.6.7

Output Clock Start and Stop

Output clocks can be stopped high or low or high-impedance.

One use for this behavior is to ensure “glitchless”

output clock operation while the output is reconfigured or phase aligned with some other signal.

Each output has an OCxSTOP register with fields to control this behavior. The OCxSTOP.MODE field specifies

whether the output clock signal stops high, low, or high-impedance. The OCxSTOP.SRC field specifies the source

of the stop signal. Options include control bits or one of the GPIO pins. When OCxSTOP.SRC=0001 the output clock

is stopped when the corresponding bit is set in the STOPCR registers OR the MCR1.STOP bit is set.

When the stop mode is Stop High (OCxSTOP.MODE=x1) and the stop signal is asserted, the output clock is stopped

after the next rising edge of the output clock. When the stop mode is Stop Low (OCxSTOP.MODE=x0) and the stop

signal is asserted, the output clock is stopped after the next falling edge of the output clock. When the output is

stopped, the output driver can optionally go high-impedance (OCxSTOP.MODE=1x). Internally the clock signal

continues to toggle while the output is stopped. When the stop signal is deasserted, the output clock resumes on the

opposite edge that it stopped on. Low-speed output clocks can take long intervals before being stopped after the

stop signal goes active. For example, a 1 Hz output could take up to 1 second to stop.

When OCxCR2.POL=1 the output stops on the opposite polarity that is specified by the OCxSTOP.MODE field.

Generally OCxCR1.MSDIV must be > 0 for this function to operate correctly since MSDIV=0 bypasses the start-stop

circuits.

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