DS20006554A datasheet(13/94 Pages) MICROCHIP

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ZL30260-ZL30263

Data Sheet

DS20006554A

5.4

Input Signal Format Configuration

Input clocks IC1, IC2 and IC3 are enabled by setting the enable bits in the ICEN register. The power consumed by a

differential receiver is shown in Table 6. The electrical specifications for these inputs are listed in Table 9. Each input

clock can be configured to accept nearly any differential signal format by using the proper set of external components

(see Figure 15). To configure these differential inputs to accept single-ended CMOS signals, connect the single-

ended signal to the ICxP pin, and connect the ICxN pin to a capacitor (0.1

F or 0.01F) to VSS. Each ICxP and ICxN

pin is internally biased to approximately 1.3V. If an input is not used, both ICxP and ICxN pins can be left floating.

Note that the IC3N pin is not present. A differential signal can be connected to IC3P by AC-coupling the POS trace

to IC3P and terminating the signal on the driver side of the coupling cap.

5.5

APLL Configuration

5.5.1

APLL Input Frequency

The frequencies of all enabled input clocks (ICx and XA) associated with the APLL must divide to a common APLL

phase-frequency detector (PFD) frequency from 9.72MHz to 156.25MHz. In this mode the input high-speed dividers

(ICxCR1.HSDIV) can be used to divide the ICx frequencies by 1, 2, 4 or 8 and the XA divider (MCR2. XODIV2) can

be used to divide the XA frequency by 1 or 2. The polarity of an ICx input signal can be inverted by setting

ICxCR1.POL.

5.5.2

APLL Input Monitors

Each of the APLL’s four inputs—IC1, IC2, IC3 and XA—have a simple activity monitor. If the monitor counts

approximately four (eight if the input clock is doubled) APLL feedback clock cycles without seeing an input clock

edge, the input is declared invalid and the corresponding ICxSR.ICV bit or XASR.ICV bit is set to 0. The input clock

is declared valid, and the corresponding ICxSR.ICV bit or XASR.ICV bit is set to 1, when the input clock has no

missing edges in an interval specified by the corresponding ICxCR1.VALTIME or XACR1.VALTIME field. The XASR

and ICxSR registers provide real-time and latched status bits indicating the state of each input.

The feedback clock to use for each input monitor is specified by the MCR2.XAMCK and MCR2.ICxMCK bits.

5.5.3

APLL Input Selection

The APLL can lock to any of inputs IC1 through IC3, a clock signal on XA (optionally clock-doubled), or the crystal

driver circuit (optionally clock-doubled) when a crystal is connected to XA and XB.

The input to the APLL can be controlled by a register field, a GPIO pin, or a simple input activity monitor. When

ACR3.EXTSW=0 and ACR3.INMON=0, the ACR3.APLLMUX register field controls the APLL input mux.

When ACR3.EXTSW=1, a GPIO pin controls the APLL input mux. When the GPIO pin is low, the mux selects the

input specified by ACR3.APLLMUX. When the GPIO pin is high, the mux selects the input specified by

ACR3.ALTMUX. ACR1.EXTSS specifies which GPIO pin controls this behavior.

When ACR3.EXTSW=0 and ACR3.INMON=1, an input monitor (see section 5.5.2) controls the APLL input mux.

When the monitor for the input specified by ACR3.APLLMUX says that input is valid (ICxSR.ICV=1 or XASR.ICV=1),

the mux selects the input specified by ACR3.APLLMUX otherwise the mux selects the input specified by

ACR3.ALTMUX.

The APLLSR.SELREF real-time status field indicates

the APLL’s selected reference.

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