DS20006554A datasheet(49/94 Pages) MICROCHIP

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ZL30260-ZL30263

Data Sheet

DS20006554A

XASR

XA Input Status Register

4Ch

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

—

XAVIE

XAVL

XAV

—

Default

The fields in the register are the same as the fields in the ICxSR registers except they apply to the XA input.

ICxSR

Input Clock Status Register

IC1: 4Dh, IC2: 4Eh, IC3: 4Fh

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

—

ICVIE

ICVL

ICV

—

Default

Bit 3: Input Clock Valid Interrupt Enable (ICVIE). This bit enables the ICxSR.ICVL latched status bit to send an

interrupt request into device’s interrupt logic.

0 = Interrupt is disabled

1 = Interrupt is enabled

Bit 2: Input Clock Valid Latched (ICVL). This latched status bit is set to 1 when the ICxSR.ICV status bit changes

state (set or cleared). This bit is cleared when written with a 1 and not set again until the ICxSR.ICV bit changes state

again. This bit can be the source of an interrupt request. See section 5.5.2.

0 = ICxSR.ICV bit has not changed state since last cleared

1 = ICxSR.ICV bit has changed state since last cleared

Bit 1: Input Clock Valid (ICV). This real-time status bit is high when the input clock monitor indicates the input is

valid. See section 5.5.2.

0 = The input clock is not valid

1 = The input clock is valid

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