SST26VF080AT-80ESLASHMF datasheet(32/72 Pages) MICROCHIP

32 / 72 page

 2019-2021 Microchip Technology Inc.

DS20006203C-page 32

SST26VF080A

5.23

Write Suspend During Sector

Erase or Block Erase

Issuing a Write Suspend instruction during Sector

Erase or 32-Kbyte Block Erase or 64-Kbyte Block

Erase allows the host to program or read any sector

that was not being erased. The device will ignore any

programming commands pointing to the suspended

sector(s). Any attempt to read from the suspended sec-

tor(s) will output unknown data because the Sector or

32-Kbyte Block Erase or 64-Kbyte Block Erase will be

incomplete.

To execute a Write Suspend operation, the host drives

CE# low, sends the Write Suspend command cycle

(B0H), then drives CE# high. The Configuration

by changing the WSE bit from ‘0’ to ‘1’, but the device

will not accept another command until it is ready. To

determine when the device will accept a new

command, poll the BUSY bit in the STATUS register or

wait TWS.

5.24

Write Suspend During Page

Programming or SPI Quad Page

Programming

Issuing a Write Suspend instruction during Page

Programming allows the host to erase or read any

sector that is not being programmed. Erase commands

pointing to the suspended sector(s) will be ignored. Any

attempt to read from the suspended page will output

unknown data because the program will be incomplete.

To execute a Write Suspend operation, the host drives

CE# low, sends the Write Suspend command cycle

(B0H), then drives CE# high. The Configuration regis-

ter indicates that the programming has been sus-

pended by changing the WSP bit from ‘0’ to ‘1’, but the

device will not accept another command until it is ready.

To determine when the device will accept a new com-

mand, poll the BUSY bit in the STATUS register or wait

TWS.

5.25

Write Resume

Write Resume restarts a write command that was sus-

pended, and changes the suspend Status bit in the

Configuration register (WSE or WSP) back to ‘0’.

To execute a Write Resume operation, the host drives

CE# low, sends the Write Resume command cycle

(30H), then drives CE# high. To determine if the inter-

nal, self-timed write operation is completed, poll the

BUSY bit in the STATUS register, or wait the specified

time TSE, TBE or TPP for Sector-Erase, Block-Erase, or

Page-Programming, respectively. The total write time

before suspend and after resume will not exceed the

uninterrupted write times TSE, TBE or TPP.

5.26

Read Security ID

The Read Security ID operation is supported in both

SPI and SQI modes. To execute a Read Security ID

(SID) operation in SPI mode, the host drives CE# low,

sends the Read Security ID command cycle (88H), two

address cycles, and then one dummy cycle. To execute

a Read Security ID operation in SQI mode, the host

drives CE# low and then sends the Read Security ID

command, two address cycles, and three dummy

cycles.

After the dummy cycles, the device outputs data on the

falling edge of the SCK signal, starting from the speci-

fied address location. The data output stream is contin-

uous through all SID addresses until terminated by a

low-to-high transition on CE#. See Table 5-5 for the

Security ID address range.

5.27

Program Security ID

The Program Security ID instruction programs one to

2032 bytes of data in the user-programmable, Security

ID space. This Security ID space is one-time-program-

mable (OTP). The device ignores a Program Security

ID instruction pointing to an invalid or protected

address, see Table 5-5. Prior to the program operation,

execute WREN.

To execute a Program SID operation, the host drives

CE# low, sends the Program Security ID command

cycle (A5H), two address cycles, the data to be pro-

grammed, then drives CE# high. The programmed data

must be between 1 to 256 bytes and in whole-byte

increments.

The device handles shifting of more than 256 bytes of

data by maintaining the last 256 bytes of data as the

correct data to be programmed. If the target address for

the Program Security ID instruction is not the beginning

of the page boundary, and the number of data input

exceeds or overlaps the end of the address of the page

boundary, the excess data inputs wrap around and will

be programmed at the start of that target page.

The Program Security ID operation is supported in both

SPI and SQI mode. To determine the completion of the

internal, self-timed Program SID operation, poll the

BUSY bit in the software STATUS register, or wait

TPSID for the completion of the internal self-timed

Program Security ID operation.

SST26VF080AT-80E/MF Datasheet(PDF) 32 Page - Microchip Technology

SST26VF080AT-80E/MF Datasheet(HTML) 32 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

Datasheet Download

Link URL