SST26VF080AT-80ESLASHMF datasheet(10/72 Pages) MICROCHIP

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DS20006203C-page 10

SST26VF080A

4.6.1

BUSY

The BUSY bit determines whether there is an internal

erase or program operation in progress. A ‘1’ for the

BUSY bit indicates the device is busy with an operation

in progress. A ‘0’ indicates the device is ready for the

next valid operation.

4.6.2

WRITE ENABLE LATCH (WEL)

The Write Enable Latch bit indicates the status of the

internal memory Write Enable Latch. If the Write

Enable Latch bit is set to ‘1’, it indicates the device is

write-enabled. If the bit is set to ‘0’ (Reset), it indicates

the device is not write-enabled and does not accept

any memory write (program/erase) commands. The

Write Enable Latch bit is automatically reset under the

following conditions:

• Power-Up

• Write Disable (WRDI) instruction completion

• Page Program instruction completion

• Sector Erase instruction completion

• Block Erase instructions (32-Kbyte and 64-Kbyte)

completion

• Chip Erase instruction completion

• Write STATUS Register instruction completion

• Software or hardware Reset

• Lock-Down Protection Setting instruction comple-

tion

• Program Security ID instruction completion

• Lockout Security ID instruction completion

• Write-Suspend instruction

• SPI Quad Page program instruction completion

4.6.3

BLOCK PROTECTION (BP3, BP2,

BP1, BP0)

The Block Protection (BP3, BP2, BP1, BP0) bits define

the size of the memory area, as defined in Table 4-4, to

be software-protected against any memory write (pro-

gram or erase) operations.

The Write STATUS Register (WRSR) instruction is used

to program the BP3, BP2, BP1 and BP0 bits as long as

WP# pin is high or the Block Protect Lock (BPL) bit is

‘0’. Chip Erase can only be executed if Block Protection

bits are ‘0’. After power-up, BP3, BP2, BP1 and BP0

are set to defaults specified in Table 4-4.

4.6.4

BLOCK PROTECTION LOCK-DOWN

(BPL)

WP# pin driven low (VIL), IO bit = 0 and WPEN bit = 1

enable the Block Protection Lock-Down (BPL) bit.

When BPL is set to ‘1’, it prevents any further alteration

of the BPL, BP3, BP2, BP1, and BP0 bits. When the

WP# pin is driven high (VIH), the BPL bit has no effect

and its value is “don’t care”. After power-up and

hardware Reset, the BPL bit is reset to ‘0’.

TABLE 4-4:

SOFTWARE STATUS REGISTER BLOCK PROTECTION

Protected Level

STATUS Register Bit

Protected Memory Address

BP3

BP2

BP1

BP0

8 Mbit

None

Upper 1/16

F0000H-FFFFFH

Upper 1/8

E0000H-FFFFFH

Upper 1/4

C0000H-FFFFFH

Upper 1/2

80000H-FFFFFH

All

00000H-FFFFFH

All

00000H-FFFFFH

All

00000H-FFFFFH

Note 1: X = “Don’t care” (Reserved) default is ‘0’.

2: Default at power-up for BP3, BP2, BP1 and BP0 is ‘0111’.

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