SST26VF080AT-80ESLASHMF datasheet(7/72 Pages) MICROCHIP

7 / 72 page

 2019-2021 Microchip Technology Inc.

DS20006203C-page 7

SST26VF080A

4.3

Security ID

SST26VF080A offers a 2-Kbyte Security ID (Sec ID)

feature. The Security ID space is divided into two parts:

one factory-programmed, 128-bit segment, and one

user-programmable segment.

The factory-programmed segment is programmed

during part manufacture with a unique number and

cannot be changed. The user-programmable segment

is left unprogrammed for the customer to program as

desired.

Use the Program Security ID (PSID) command to

program the Security ID using the address shown in

Table 5-5. The Security ID can be locked using the

Lockout Security ID (LSID) command. This prevents

any future write operations to the Security ID.

The factory-programmed portion of the Security ID can

not be programmed by the user; neither the

factory-programmed nor user-programmable areas

can be erased.

4.4

Hold Operation

The HOLD# pin pauses active serial sequences

without resetting the clocking sequence. This pin is

active after every power-up and only operates

during SPI single-bit and dual-bit modes.

SST26VF080A ships with the IOC bit set to ‘0’ and the

HOLD# pin function enabled. The HOLD# pin is always

disabled in SQI mode and only works in SPI single-bit

and dual-bit read mode.

To activate the Hold mode, CE# must be in active-low

state. The Hold mode begins when the SCK active-low

state coincides with the falling edge of the HOLD#

signal. The Hold mode ends when the HOLD# signal’s

rising edge coincides with the SCK active-low state.

If the falling edge of the HOLD# signal does not

coincide with the SCK active-low state, then the device

enters Hold mode when the SCK next reaches the

active-low state. Similarly, if the rising edge of the

HOLD# signal does not coincide with the SCK

active-low state, then the device exits Hold mode when

the SCK next reaches the active-low state. See

Figure 4-3.

Once the device enters Hold mode, SO will be in

high-impedance state while SI and SCK can be VIL or

VIH.

If CE# is driven active-high during a Hold condition, it

resets the internal logic of the device. As long as

HOLD# signal is low, the memory remains in the Hold

condition. To resume communication with the device,

HOLD# must be driven active-high, and CE# must be

driven active-low.

FIGURE 4-3:

HOLD CONDITION WAVEFORM

4.5

Reset Operation

If the RST#/HOLD#SIO3 pin is used as a Reset pin,

RST# pin provides a hardware method for resetting the

device. SST26VF080A supports both hardware and

software Reset operation. Hardware Reset is only

allowed using SPI x1 and x2 protocol. Software Reset

commands 66H and 99H are supported in all protocols.

See Table 4-2 and for Figure 4-4 for hardware and

software Reset functionality.

Depending on the prior operation, the Reset timing may

vary. Recovery from a write operation requires more

latency time than recovery from other operations.

4.5.1

HARDWARE RESET OPERATION

To configure the RESET#/HOLD#/SIO3 pin as a

RESET# pin, bit 6 of the Configuration register must be

set to ‘1’. The factory default setting of bit 6 is

‘0’-HOLD# pin enabled. This is a nonvolatile bit, so the

power-down. Driving the RESET# pin high puts the

device in normal operating mode. The RESET# pin

must be driven low for a minimum of TRST time to reset

the device. The SIO1 pin (SO) is in high-impedance

state while the device is in Reset. A successful Reset

operation will reset the protocol to SPI mode, STATUS

WEL = 0, BP0 = 1, BP1 = 1, BP2 = 1 and BPL = 0;

reset the burst length to 8 bytes. Reset during an active

program or erase operation aborts the operation and

data of the targeted address range may be corrupted or

lost due to the aborted erase or program operation.

Active

Hold

Active

Hold

Active

SCK

HOLD#

Note:

A device Reset during an active program

or erase operation aborts the operation

and data of the targeted address range

may be corrupted or lost due to the

aborted erase or program operation.

SST26VF080AT-80E/MF Datasheet(PDF) 7 Page - Microchip Technology

SST26VF080AT-80E/MF Datasheet(HTML) 7 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

Datasheet Download

Link URL