Z8F082ASH020SC datasheet(130/244 Pages) ZILOG

130 / 244 page

PS024705-0405

P R E L I M I N A R Y

Analog-to-Digital Converter

Z8 Encore! XP® F08xA Series

Product Specification

112

3. Write the ADC Control/Status Register 1 to configure the ADC

–

Write to BUFMODE[2:0] to select SINGLE-ENDED or DIFFERENTIAL mode, as

well as unbuffered, buffered, 20x buffered gain (in differential mode only) or

transimpedance mode

–

If the alarm function is required, set ALMHEN and/or ALMLEN

–

Write the REFSELH bit of the pair {REFSELH, REFSELL} to select the internal

voltage reference level or to disable the internal reference. The REFSELH bit is

contained in the ADC Control/Status Register 1.

4. Write to the ADC Control Register 0 to configure the ADC for continuous conversion.

The bit fields in the ADC Control register may be written simultaneously:

–

Write to the ANAIN[3:0] field to select from the available analog input sources

(different input pins available depending on the device)

–

Set CONT to 1 to select continuous conversion.

–

If the internal VREF must be output to a pin, set the REFEXT bit to 1. The

internal voltage reference must be enabled in this case.

–

Write the REFSELL bit of the pair {REFSELH, REFSELL} to select the internal

voltage reference level or to disable the internal reference. The REFSELL bit is

contained in ADC Control Register 0.

–

Set CEN to 1 to start the conversions.

5. When the first conversion in continuous operation is complete (after 5129 system

clock cycles, plus the 40 cycles for power-up, if necessary), the ADC control logic

performs the following operations:

–

CEN

resets to 0 to indicate the first conversion is complete. CEN remains 0 for all

subsequent conversions in continuous operation.

–

An interrupt request is sent to the Interrupt Controller to indicate the conversion is

complete.

6. The ADC writes a new data result every 256 system clock cycles. For each completed

conversion, the ADC control logic performs the following operations:

–

Writes the 11-bit two’s complement result to {ADCD_H[7:0], ADCD_L[7:5]}.

–

If the high and low alarms are disabled, sends an interrupt request to the Interrupt

Controller denoting conversion complete.

–

If the high alarm is enabled and the ADC value is higher than the alarm threshold,

generates an interrupt.

–

If the low alarm is enabled and the ADC value is lower than the alarm threshold,

generates an interrupt.

7. To disable continuous conversion, clear the CONT bit in the ADC Control Register

to 0.

Z8F082ASH020SC Datasheet(PDF) 130 Page - Zilog, Inc.

Z8F082ASH020SC Datasheet(HTML) 130 Page - Zilog, Inc.

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