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AS3977 Datasheet(PDF) 16 Page - ams AG |
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AS3977 Datasheet(HTML) 16 Page - ams AG |
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16 / 47 page ![]() www.austriamicrosystems.com/AS3977 Revision 3.6 16 - 47 AS3977 Data Sheet - Ti m i n g C h a r a c t e r i s t i c s 7.1 Timing Parameters Table 18. Timing Parameters Symbol Parameter Condition Min Typ Max Units General BRSDI Bit rate 2 Mbps tCH Clock high time 250 ns tCL Clock low time 250 ns Write timing tDIS Data in setup time 20 ns tDIH Data in hold time 10 ns tEH Enable hold time 20 ns Read timing tDIHZ Data in to high impedance delay time for the µC to release the DATAIO bus 45 ns tDOS Data out setup time 130 ns tDOH Data out hold time 135 ns tDOD Data out delay 80 ns tDOHZ Data out to high impedance delay time for the SDI to release the DATAIO bus 80 ns Timing parameters when leaving the Power Down Mode (for determination of CLK polarity and MCCLK behavior) tCS Clock setup time (CLK polarity) Setup time of CLK with respect to ENABLE rising edge 20 ns tCHD Clock hold time (CLK polarity) Hold time of CLK with respect to ENABLE rising edge 20 ns tMS Data in setup time (MCCLK behavior) DATAIO setup time with respect to ENABLE rising edge 20 ns tMH Data in hold time (MCCLK behavior) DATAIO hold time with respect to ENABLE rising edge 20 ns |
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