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STM32H750VB Datasheet(PDF) 295 Page - STMicroelectronics |
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STM32H750VB Datasheet(HTML) 295 Page - STMicroelectronics |
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295 / 335 page ![]() DS12556 Rev 5 295/334 STM32H750VB STM32H750ZB STM32H750IB STM32H750XB Electrical characteristics (rev V) 311 Figure 97. USART timing diagram in Master mode 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. Figure 98. USART timing diagram in Slave mode ai14136c CPHA= 0 MOSI OUTPUT MISO INP UT CPHA= 0 LSB OUT LSB IN CPOL=0 CPOL=1 B I T1 OUT NSS input tc(SCK) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) th(MI) High CPHA=1 CPHA=1 CPOL=0 CPOL=1 tsu(MI) tv(MO) th(MO) MSB IN BIT6 IN MSB OUT MSv41658V1 NSS input CPHA=0 CPOL=0 CPHA=0 CPOL=1 MISO output MOSI input tsu(SI) th(SI) tw(SCKL) tw(SCKH) tc(SCK) tr(SCK) th(NSS) tdis(SO) tsu(NSS) ta(SO) tv(SO) Next bits IN Last bit OUT First bit IN First bit OUT Next bits OUT th(SO) tf(SCK) Last bit IN |
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