STM32H750VB datasheet(299/335 Pages) STMICROELECTRONICS

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DS12556 Rev 5

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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB

Electrical characteristics (rev V)

311

I2S Interface characteristics

Unless otherwise specified, the parameters given in Table 204 for I2S are derived from tests

performed under the ambient temperature, fPCLKx frequency and VDD supply voltage

conditions summarized in Table 120: General operating conditions, with the following

configuration:



Output speed is set to OSPEEDRy[1:0] = 10



Capacitive load CL = 30 pF



Measurement points are done at CMOS levels: 0.5VDD



IO Compensation cell activated.



HSLV activated when VDD ≤ 2.7 V



VOS level set to VOS1

Refer to Section 7.3.15: I/O port characteristics for more details on the input/output alternate

function characteristics (CK,SD,WS).

Table 204. I2S dynamic characteristics(1)

1. Guaranteed by characterization results.

Symbol

Parameter

Conditions

Min

Max

Unit

fMCK

I2S main clock output

256x8K

256FS

MHz

fCK

I2S clock frequency

Master data

64FS

MHz

Slave data

64FS

tv(WS)

WS valid time

Master mode

th(WS)

WS hold time

Master mode

tsu(WS)

WS setup time

Slave mode

th(WS)

WS hold time

Slave mode

tsu(SD_MR)

Data input setup time

Master receiver

tsu(SD_SR)

Slave receiver

th(SD_MR)

Data input hold time

Master receiver

th(SD_SR)

Slave receiver

tv(SD_ST)

Data output valid time

Slave transmitter (after enable

edge)

-17

tv(SD_MT)

Master transmitter (after

enable edge)

-3

th(SD_ST)

Data output hold time

Slave transmitter (after enable

edge)

th(SD_MT)

Master transmitter (after

enable edge)

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