STM32L053C8 datasheet(135/136 Pages) STMICROELECTRONICS

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DS10152 Rev 9

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STM32L053x6 STM32L053x8

Revision history

135

11-

Sep-

2017

Memories and I/Os moved after Core in Features.

Removed column "I/O operation" from Table 2: Functionalities depending on

the operating power supply range and added note related to GPIO speed.

Updated VDD_USB in Section 3.4.1: Power supply schemes.

Updated Figure 30: 12-bit buffered/non-buffered DAC and added note below

figure.

In Section 5: Memory mapping, replaced memory mapping schematic by

reference to the reference manual.

Updated minimum and maximum values of I/O weak pull-up equivalent resistor

(RPU) and weak pull-down equivalent resistor (RPD) in Table 58: I/O static

characteristics.

Updated minimum and maximum values of NRST weak pull-up equivalent

resistor (RPU) in Table 61: NRST pin characteristics.

Removed Table 90: USART/LPUART characteristics.

Updated Figure 40: TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine

pitch ball grid array package outline.

Updated note below marking schematics.

27-Jun-

2019

Added UFQFPN48 package.

Updated Arm logo and added Arm word mark notice in Section 1: Introduction.

Removed Cortex and USB logos.

Updated Table 4: Functionalities depending on the working mode (from

Run/active down to standby) to change I2C functionality to disabled in Low-

power Run and Low-power Sleep modes.

Updated VDD_USB description in Section 3.4.1: Power supply schemes.

Replaced

LCD_VLCD2 by LCD_VLCD1 in Section 3.13.2: VLCD voltage

monitoring.

Changed USARTx_RTS, USARTx_RTS_DE into USARTx_RTS/USARTx_DE,

and LPUART1_RTS, LPUART1_RTS_DE into LPUART1_RTS/LPUART1_DE

in Section 4: Pin descriptions. In Table 15: STM32L053x6/8 pin definitions

changed PB2 and PB12 additional functions to LCD_VLCD2 and LCD_VLCD1,

respectively.

Updated VDD_USB and note 2. in Table 24: General operating conditions.

Updated tAF maximum value for range 1 in Table 71: I2C analog filter

characteristics.

Updated Figure 40: TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine

pitch ball grid array package outline, Figure 41: TFBGA64 – 64-ball, 5 x 5 mm,

0.5 mm pitch, thin profile fine pitch ball ,grid array recommended footprint and

Figure 82: TFBGA64 recommended PCB design rules (0.5 mm pitch BGA).

Updated paragraph introducing all package marking schematics to add the new

sentence “The printed markings may differ depending on the supply chain”.

Added UFQFPN48 package marking example.

Table 86. Document revision history (continued)

Date

Revision

Changes

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