ICL7135CSLASHD datasheet(9/13 Pages) MAXIM

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the signal integration period should be an integral multiple

of the power line cycles.

CLK

LINE

CLK

Reading Rate (in readings per second) =

40,002

x 10,000

for maximum normal mode rejection =

Where fLINE is the line frequency, normally 50Hz or 60Hz

and N is the number of line cycles that occur during a

signal integration period. For maximum normal mode

rejection, N should be an integer.

For 60Hz rejection, suitable clock frequencies include

300kHz, 200kHz, 150kHz, 120kHz, 100kHz, and 75kHz.

Suitable frequencies for use with 50Hz power include

250kHz , 1662/3kHz, 125kHz, and 100kHz. The two most

common clock frequencies are 120kHz (3 readings per

second) and 100kHz (21/2 readings per second). Note

that a 100kHz clock frequency rejects both 50Hz and

60Hz normal mode signals.

The maximum clock rate is limited by the maximum rate

at which the digital logic will correctly function (typically

2MHz), and by the speed of response of the comparator.

The comparator delay, about 3µs, has the same effect on

the measurement result as does an offset voltage with

the same polarity of the input signal. At the recommended

clock frequency of 120kHz, this small offset is slightly less

than 1/2 count. At higher clock frequencies the value of

the speedup resistor in series with the integration capaci-

tor (normally 27Ω) should be increased. At frequencies

above 120kHz, ringing on the integrator output may cause

nonlinearities in the first few counts.

The minimum clock frequency is limited by the leakage

of the auto-zero and reference capacitors. While seldom

desired, measurement cycles as long as 10 seconds can

be performed with negligible error at room temperature.

Figures 8A and 8B show two methods of generating a

suitable clock signal for the ICL7135.

Application Hints

Grounds

As with all sensitive analog circuitry, it is important to

keep the Digital Ground separate from the .analog ground

(called Analog Common on the ICL7135) to minimize

errors caused by the coupling of noise from the digital

circuitry into the sensitive analog section. Analog Common

should be connected to Digital Ground at only one point,

and return currents from digital loads must not flow

through the analog ground lines. Avoid any unnecessary

current flow in the analog ground path.

Single 5V Supply Operation

The ICL7135 normally uses ±5V supplies, however, in

some applications the negative supply is not needed.

Specifically, the negative 5V supply is not required if

the input signal can be referenced to the center of the

ICL7135’s common mode voltage range AND the signal

voltage is less than ±1.5V. The integrator swing must be

reduced, and there will be a slight increase in system

noise and nonlinearity. See Figure 9 for recommended

component values.

Figure 8A. LM311 Clock Source

Figure 9. Single +5V Supply Operation

Figure 8B. Crystal Oscillator Clock Source

ICL7135

41/2 Digit A/D Converter with

Multiplexed BCD Outputs

www.maximintegrated.com

Maxim Integrated │ 9

16kΩ

0.22µF

1kΩ

30kΩ

390pF

+5V

56kΩ

ICL7135

CLOCK IN

LM311

22MΩ

ICL7135

CLOCK IN

100kHz OR

120kHz

TUNING

FORK

CRYSTAL

330kΩ

10pF

5pF

MAX4069

CMOS

INVERTOR

ANALOG COMMON

27Ω

100kΩ

SET VREF = 1.000V

VREF IN

2.5V

SIGNAL

INPUT

100kΩ

1.0µF

2.0µF

1µF

0.1µF

INT. OUT

RUN/HOLD

V-

-5V

REFERENCE

OVERRANGE

STROBE

UNDERRANGE

REF. CAP-

REF. CAP+

BUSY

A-Z IN

BUFF OUT

POLARITY

CLOCK IN

DIGITAL GND

CLOCK

120kHz

IN LO

LSD D1

IN HI

V+

MSD D5

LSB B1

MSB B8

ICL7135

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