Detailed Description

General Operation

The ICL7135 is divided into an Analog section and a

Digital section. The digital section includes the counters,

input and output interfaces, and control logic which controls

the timing of each measurement cycle. Each measurement

is divided into four phases: 1) auto-zero (AZ), 2) signal

integrate (INT), 3) reference deintegrate (DE), and 4) zero

integrator (ZI). The digital section controls the operation

of the analog section during each of these phases, using

counters and the state of the comparator to determine

when to start each of the four phases.

Auto-Zero Phase

During auto-zero Input HI and Input LO are disconnected

from the input pins and are internally shorted to Analog

COMMON. The output of the comparator is connected

to the inverting input of the Integrator, and at the same

time the non-inverting input of the integrator is connected

to the input of the buffer. This feedback loop charges the

voltages of the buffer amplifier, integrator, and comparator.

Also during auto-zero,the reference capacitor is

connected to the voltage reference and is charged to the

reference voltage. The auto-zero cycle is a minimum of

9800 clock cycles, except after an over-range reading.

After an over-range, the extended zero integrate phase

reduces the auto-zero phase to 3800 clock cycles.

Signal Integrate Phase

At the end of the auto-zero phase the auto-zero loop is

opened, and the Input High and Input Low are switched

to the external pins IN-HI and IN-LO. The analog section

integrates the differential voltage between Input High

and Input Low. The differential voltage must be within

the ICL7135’s common mode range. The voltage on the

integrator capacitor at the end of signal integrate is directly

proportional to the differential voltage between Input High

and Input Low, and is also directly proportional to the

length of the signal integrate phase. The signal integrate

phase lasts precisely 10,000 clock cycles. At the end of

this phase the input signal polarity is determined.

De-Integrate Phase

At the end of signal integrate, Input High and Input Low

are disconnected from the external pins. The integrator

non-inverting input pin is then internally connected to

Analog Common and the buffer input is connected to

one side of the reference capacitor. The other side of

the reference capacitor is connected to Analog Common.

The polarity at the output of the integrator (as detected

by the comparator at the end of signal integrate phase)

determines which terminal of the reference capacitor is

connected to the buffer input. The reference capacitor

polarity is chosen so that the integrator output will always

return towards Analog Common. Since the reference

capacitor was charged to the reference voltage during

the auto-zero phase, the integrator input voltage is now

the reference voltage. The De-Integrate phase lasts for

20,001 counts, or until the comparator detects that the

integrator output has crossed zero, whichever occurs first.

The time required to return to zero is proportional to the

input signal and is inversely proportional to the reference

voltage. The number of clock cycles required to return to

zero is counted by the digital section and is latched as the

measurement result.

IN

REF

V

Displayed reading = 10,000 x

V

Zero Integrator Phase

The last of the four phases is the zero integrator phase.

The non-inverting input of the integrator is internally shorted

to Analog Common and the buffer input is internally

connected to the output of the comparator. This closes

a loop that forces the integrator output to zero. Normally

this phase lasts only 100 to 200 counts, sufficient time

to remove the small residual charge on the integrator

capacitor caused by the comparator delay and the one

count delay created by sampling the comparator output

only once per clock cycle. However, an overrange condition

will exist when the integrator output does not return to

zero by the end of the De-Integrate phase, and can leave

a residual voltage on the integrator capacitor. In this case,

the Zero Integrator phase is increased to 6200 counts to

ensure that the integrator capacitor is fully discharged

before the next measurement cycle is started.

Analog Section

Analog COMMON

Analog COMMON is the Analog ground reference for the

ICL7135. If Input Low is at a voltage other than Analog

Figure 1. ICL7135 Test Circuit

ICL7135

Multiplexed BCD Outputs

www.maximintegrated.com

Maxim Integrated │ 4

ANALOG COMMON

27Ω

100kΩ

100kΩ

100kΩ

ANALOG

GND

SIGNAL

INPUT

100kΩ

0.47µF

1.0µF

1µF

0.1µF

INT. OUT

RUN/HOLD

1

2

28

27

V-

-5V

+5V

REFERENCE

OVERRANGE

STROBE

UNDERRANGE

3

4

26

25

REF. CAP-

REF. CAP+

BUSY

5

6

24

23

A-Z IN

BUFF OUT

POLARITY

CLOCK IN

DIGITAL GND

OV

CLOCK

IN

120kHz

7

8

22

21

IN LO

LSD D1

9

20

IN HI

D2

10

19

V+

D3

11

18

MSD D5

LSB B1

B2

D4

MSB B8

B4

12

17

13

16

14

15

ICL7135